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81. 发明申请

US20180358361A1 METHOD FOR MAKING DRAM WITH RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) INCLUDING A SUPERLATTICE 审中-公开
公开(公告)号：US20180358361A1
公开(公告)日：2018-12-13
申请号：US16007186
申请日：2018-06-13
申请人： ATOMERA INCORPORATED
发明人： KALIPATNAM VIVEK RAO
IPC分类号： H01L27/108 , H01L29/10 , H01L29/08 , H01L29/15
CPC分类号： H01L29/152 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0847 , H01L29/1033 , H01L29/1037 , H01L29/1054 , H01L29/15 , H01L29/4236 , H01L29/66704 , H01L29/7825
摘要： A method for making a semiconductor device may include forming at least one memory array including a plurality of recessed channel array transistors (RCATs) on a substrate, and forming periphery circuitry adjacent the at least one memory array and comprising a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, and a first superlattice extending between the source and drain regions in the channel region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may be over the first superlattice and between the source and drain regions.

82. 发明申请

US20180052196A1 SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAGE MEASUREMENT CIRCUITRY 审中-公开
公开(公告)号：US20180052196A1
公开(公告)日：2018-02-22
申请号：US15678616
申请日：2017-08-16
申请人： ATOMERA INCORPORATED
发明人： Richard Stephen ROY
IPC分类号： G01R31/28 , H01L29/15 , H01L27/092 , H01L29/78
CPC分类号： G01R31/2831 , G01R31/2644 , G01R31/2648 , G01R31/275 , G01R31/2894 , G01R31/31924 , G01R31/31932 , G11C11/4078 , G11C11/4087 , G11C29/50004 , H01L22/34 , H01L27/092 , H01L27/10897 , H01L29/105 , H01L29/152 , H01L29/16 , H01L29/7843 , H01L29/7849 , H03F3/45183 , H03F2200/453 , H03F2203/45361 , H03F2203/45368
摘要： A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.

83. 发明授权

US09899479B2 Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods 有权
公开(公告)号：US09899479B2
公开(公告)日：2018-02-20
申请号：US15154296
申请日：2016-05-13
申请人： Atomera, Incorporated
发明人： Robert J. Mears , Hideki Takeuchi
IPC分类号： H01L29/15 , H01L27/092 , H01L29/06 , H01L21/8238 , H01L29/66 , H01L29/423 , H01L21/8234 , H01L29/78 , H01L29/10
CPC分类号： H01L29/157 , H01L21/823412 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L27/088 , H01L27/092 , H01L27/0922 , H01L29/0638 , H01L29/1045 , H01L29/105 , H01L29/1054 , H01L29/1083 , H01L29/152 , H01L29/155 , H01L29/158 , H01L29/42384 , H01L29/66537 , H01L29/7833
摘要： A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.

84. 发明申请

US20180040714A1 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS 审中-公开
公开(公告)号：US20180040714A1
公开(公告)日：2018-02-08
申请号：US15670274
申请日：2017-08-07
申请人： ATOMERA INCORPORATED
发明人： ROBERT J. MEARS , HIDEKI TAKEUCHI , MAREK HYTHA
IPC分类号： H01L29/66 , H01L29/88
CPC分类号： H01L29/7376 , H01L27/092 , H01L29/1054 , H01L29/152 , H01L29/155 , H01L29/157 , H01L29/161 , H01L29/36 , H01L29/66007 , H01L29/6603 , H01L29/66121 , H01L29/66151 , H01L29/66477 , H01L29/66545 , H01L29/66651 , H01L29/78 , H01L29/7842 , H01L29/8618 , H01L29/882
摘要： A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.

85. 发明授权

US09853106B2 Nano-structure assembly and nano-device comprising same 有权
公开(公告)号：US09853106B2
公开(公告)日：2017-12-26
申请号：US14767961
申请日：2013-07-01
申请人： SNU R&DB Foundation
发明人： Gyu Chul Yi , Hong Seok Oh
IPC分类号： H01L29/772 , H01L29/20 , F28D15/02 , H01L29/06 , H01L29/15 , H01L29/775 , H01L29/786 , H01L33/64 , H01L23/373
CPC分类号： H01L29/2003 , F28D15/02 , H01L23/373 , H01L29/0676 , H01L29/152 , H01L29/775 , H01L29/786 , H01L33/641 , H01L2924/0002 , H01L2924/00
摘要： Provided are a nano-structure assembly including an insulating substrate; and a nano-structure formed on the insulating substrate, and a nano-device including the same.

86. 发明授权

US09406845B2 Nitride semiconductor structure 有权
标题翻译：氮化物半导体结构
公开(公告)号：US09406845B2
公开(公告)日：2016-08-02
申请号：US14810433
申请日：2015-07-27
申请人： PlayNitride Inc.
发明人： Yen-Lin Lai , Jyun-De Wu
IPC分类号： H01L29/06 , H01L33/32 , H01L33/06 , H01L29/15
CPC分类号： H01L33/325 , H01L29/152 , H01L33/06
摘要： A nitride semiconductor structure including a substrate, a first type nitride semiconductor layer disposed on the substrate, an active layer disposed between the substrate and the first type nitride semiconductor layer and a second type nitride semiconductor layer disposed between the substrate and the active layer is provided. The active layer includes a first multiple quantum well structure including a plurality of first quantum well layers and a plurality of first barrier layers staggered with each other, and a second multiple quantum well structure including a plurality of second quantum well layers and a plurality of second barrier layers staggered with each other. A second type dopant is doped into at least one of the second barrier layers, and a concentration of the second dopant in the second barrier layer is higher than that of the second dopant in the second type nitride semiconductor layer.
摘要翻译：提供一种氮化物半导体结构，其包括衬底，设置在衬底上的第一氮化物半导体层，设置在衬底和第一氮化物半导体层之间的有源层和设置在衬底和有源层之间的第二氮化物半导体层。有源层包括第一多量子阱结构，其包括多个第一量子阱层和彼此交错的多个第一势垒层，以及包括多个第二量子阱层和多个第二量子阱层的第二多量子阱结构屏障层彼此交错。第二类型掺杂剂被掺杂到第二阻挡层中的至少一个中，并且第二阻挡层中的第二掺杂剂的浓度高于第二氮化物半导体层中的第二掺杂剂的浓度。

87. 发明申请

US20160149023A1 SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND REPLACEMENT METAL GATE STRUCTURE AND RELATED METHODS 有权
标题翻译：包括超级和替代金属门结构的半导体器件及相关方法
公开(公告)号：US20160149023A1
公开(公告)日：2016-05-26
申请号：US14948547
申请日：2015-11-23
申请人： MEARS TECHNOLOGIES, INC.
发明人： Robert J. Mears , Tsu-Jae King LIU , Hideki Takeuchi
IPC分类号： H01L29/778 , H01L29/66 , H01L29/06 , H01L29/15
CPC分类号： H01L29/154 , H01L29/0642 , H01L29/0653 , H01L29/1054 , H01L29/1083 , H01L29/152 , H01L29/155 , H01L29/165 , H01L29/66431 , H01L29/66545 , H01L29/66621 , H01L29/7782
摘要： A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
摘要翻译：半导体器件可以包括其中具有沟道凹槽的衬底，衬底中的多个间隔开的浅沟槽隔离（STI）区域，以及在衬底中和在一对STI区域之间间隔开的源极和漏极区域。超晶格通道可以在衬底的通道凹槽中并且在源极和漏极区域之间延伸，超晶格通道包括多个堆叠的层组，并且超晶格沟道的每组层包括层叠的基底半导体单层，其定义为基底半导体部分和限制在相邻基极半导体部分的晶格内的至少一个非半导体单层。替代门可能超过超晶格通道。

88. 发明授权

US09287362B1 Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts 有权
公开(公告)号：US09287362B1
公开(公告)日：2016-03-15
申请号：US14550069
申请日：2014-11-21
申请人： International Business Machines Corporation
发明人： Anirban Basu , Cheng-Wei Cheng , Wilfried E. Haensch , Amlan Majumdar , Kuen-Ting Shiu
IPC分类号： H01L29/775 , H01L29/15 , H01L29/78 , H01L29/66 , H01L21/321 , H01L21/28
CPC分类号： H01L29/78696 , H01L29/152 , H01L29/42392 , H01L29/66742 , H01L29/66977 , H01L29/7391 , H01L29/78642
摘要： An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.

89. 发明申请

US20150144877A1 VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS 有权
标题翻译：垂直半导体器件，包括通过停止层的超级激励器及相关方法
公开(公告)号：US20150144877A1
公开(公告)日：2015-05-28
申请号：US14550244
申请日：2014-11-21
申请人： MEARS Technologies, Inc.
发明人： Robert Mears , Hideki Takeuchi , Erwin Trautmann
IPC分类号： H01L27/088 , H01L21/324 , H01L29/165 , H01L29/10 , H01L21/8234 , H01L29/15
CPC分类号： H01L29/152 , H01L21/324 , H01L21/823412 , H01L21/823431 , H01L27/0886 , H01L29/0638 , H01L29/1054 , H01L29/1083 , H01L29/155 , H01L29/165 , H01L29/66537 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
摘要翻译：半导体器件可以包括衬底和在衬底上间隔开的多个散热片。每个翅片可以包括从基底垂直向上延伸的下半导体翅片部分，以及在下翅片部分上的至少一个超晶格穿通层。超晶格穿通层可以包括多个堆叠的层组，超晶格穿透层的每组层包括限定基极半导体部分的多个堆叠的基底半导体单层和至少一个非半导体单层约束在相邻的基底半导体部分的晶格内。每个翅片还可以包括在至少一个超晶格穿通层上并从其垂直向上延伸的上半导体翅片部分。半导体器件还可以包括在鳍片的相对端处的源极和漏极区域以及覆盖鳍片的栅极。

90. 发明授权

US07947971B2 Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains 有权
标题翻译：量子阱MOSFET通道由金属源/漏极引起的单轴应变，以及保形再生长源/漏极
公开(公告)号：US07947971B2
公开(公告)日：2011-05-24
申请号：US12756989
申请日：2010-04-08
申请人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L29/06 , H01L31/072 , H01L31/0336 , H01L31/0328 , H01L31/109
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译：所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变顶部阻挡层和量子阱的底部缓冲层。

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