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81. 发明申请

US20180254286A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 审中-公开
公开(公告)号：US20180254286A1
公开(公告)日：2018-09-06
申请号：US15971293
申请日：2018-05-04
申请人： SANDISK TECHNOLOGIES LLC
发明人： Thomas H. Lee , Igor G. Kouznetsov
IPC分类号： H01L27/11582 , H01L29/861 , G11C16/04 , H01L29/792 , H01L29/788 , H01L29/786 , H01L29/739 , H01L29/66 , H01L29/51 , H01L29/423 , H01L29/16 , H01L29/06 , H01L27/12 , G11C16/10 , G11C16/14 , H01L27/11578 , H01L27/11573 , H01L27/11568 , H01L27/11565 , H01L27/11558 , H01L27/11556 , H01L27/11551 , H01L27/11526 , H01L27/11521 , H01L27/115 , H01L27/112 , H01L27/06 , H01L23/532 , H01L23/528 , H01L21/822 , H01L21/768 , H01L21/3105 , G11C16/34 , G11C16/26 , H01L27/1158
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

82. 发明申请

US20170352704A1 CELL PILLAR STRUCTURES AND INTEGRATED FLOWS 审中-公开
公开(公告)号：US20170352704A1
公开(公告)日：2017-12-07
申请号：US15686389
申请日：2017-08-25
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Krishna K. Parat
IPC分类号： H01L27/24 , H01L29/792 , H01L27/1158 , H01L27/11553 , H01L29/66 , H01L45/00 , H01L29/788
CPC分类号： H01L27/2454 , H01L27/11553 , H01L27/1158 , H01L27/2481 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/1608
摘要： Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

83. 发明授权

US09831309B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09831309B2
公开(公告)日：2017-11-28
申请号：US15017818
申请日：2016-02-08
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hidekazu Miyairi
IPC分类号： H01L29/06 , H01L29/423 , H01L29/786 , H01L27/112 , H01L27/115 , H01L29/78 , H01L27/11553 , H01L27/1158 , H01L27/11582 , H01L27/11556
CPC分类号： H01L29/0688 , H01L27/11273 , H01L27/11553 , H01L27/11556 , H01L27/1158 , H01L27/11582 , H01L29/41733 , H01L29/4236 , H01L29/42384 , H01L29/4908 , H01L29/78642 , H01L29/7869 , H01L29/78696
摘要： A miniaturized transistor having highly stable electrical characteristics is provided. Furthermore, high performance and high reliability of a semiconductor device including the transistor is achieved. The transistor includes a first electrode, a second electrode, a third electrode, an oxide semiconductor layer, a first insulating layer, and a second insulating layer. The transistor includes a first region and a second region surrounded by the first region. In the first region, the first insulating layer, the second electrode, the oxide semiconductor layer, and the second insulating layer are stacked. In the second region, the first electrode, the oxide semiconductor layer, the second insulating layer, and the third electrode are stacked.

84. 发明授权

US09773922B1 Memory device 有权
公开(公告)号：US09773922B1
公开(公告)日：2017-09-26
申请号：US15336819
申请日：2016-10-28
申请人： UNITED MICROELECTRONICS CORP.
发明人： Po-Hsieh Lin , Chia-Fu Hsu , Bei-Zhun Syu
IPC分类号： H01L27/115 , H01L29/792 , H01L29/10 , H01L29/78 , H01L27/1158
CPC分类号： H01L29/7827 , H01L27/1158 , H01L27/11582 , H01L29/1037 , H01L29/7926
摘要： A memory device includes: a substrate; a channel layer on the substrate, in which the channel layer includes a T-shape having a horizontal portion with a first end and a second end and a vertical portion having a third end; a gate structure on a side of the vertical portion; an oxide-nitride-oxide (ONO) layer between the gate structure and the vertical portion; a source region on the first end of the horizontal portion; and a drain region on the third end of the vertical portion.

85. 发明申请

US20170236589A1 MEMORY DEVICES WITH A CONNECTING REGION HAVING A BAND GAP LOWER THAN A BAND GAP OF A BODY REGION 有权
公开(公告)号：US20170236589A1
公开(公告)日：2017-08-17
申请号：US15583411
申请日：2017-05-01
申请人： Micron Technology, Inc.
发明人： Haitao Liu , Jian Li , Chandra Mouli
IPC分类号： G11C16/14 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/161 , H01L29/08 , H01L29/16 , H01L29/20 , H01L29/22 , G11C16/04 , H01L27/11582
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/1158 , H01L27/11582 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/2003 , H01L29/22 , H01L29/7926
摘要： Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

86. 发明授权

US09698261B2 Vertical device architecture 有权
公开(公告)号：US09698261B2
公开(公告)日：2017-07-04
申请号：US14318835
申请日：2014-06-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Hao Wang , Jhon Jhy Liaw , Wai-Yi Lien , Jia-Chuan You , Yi-Hsun Chiu , Ching-Wei Tsai , Wei-Hao Wu
IPC分类号： H01L29/78 , H01L29/66 , H01L27/11582 , H01L27/06 , H01L29/788 , H01L29/792 , H01L27/1158 , H01L27/11556 , H01L21/822 , H01L27/11
CPC分类号： H01L29/7827 , H01L21/8221 , H01L27/0688 , H01L27/1104 , H01L27/11556 , H01L27/1158 , H01L27/11582 , H01L29/66666 , H01L29/7889 , H01L29/7926
摘要： The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation. In some embodiments, the vertical transistor device has a source region disposed over a semiconductor substrate. A channel region with one or more vertical channel bars is disposed over the source region. The one or more vertical channel bars have a bottom surface abutting the source region that has a rectangular shape (i.e., a shape with four sides, with adjacent sides of different length, and four right angles). A gate region is located over the source region at a position abutting the vertical channel bars, and a drain region is disposed over the gate region and the vertical channel bars. The rectangular shape of the vertical channel bars provides for a vertical device having good performance and cell area density.

87. 发明授权

US09536707B2 Etching method of multilayered film 有权
标题翻译：多层膜的蚀刻方法
公开(公告)号：US09536707B2
公开(公告)日：2017-01-03
申请号：US14817463
申请日：2015-08-04
申请人： Tokyo Electron Limited
发明人： Ryuuu Ishita , Yusuke Saitoh
IPC分类号： C03C15/00 , H01J37/32 , H01L21/311 , H01L21/3213
CPC分类号： H01J37/32165 , H01J37/32091 , H01L21/31116 , H01L21/32137 , H01L27/11553 , H01L27/1158
摘要： An etching method of etching a multilayered film includes etching a multilayered film by generating plasma within a processing vessel of a plasma processing apparatus. In the etching of the multilayered film, a first processing gas containing a hydrogen gas, a hydrogen bromide gas, a fluorine-containing gas, a hydrocarbon gas, a hydrofluorocarbon gas and a fluorocarbon gas is supplied from a first supply unit configured to supply a gas toward a central region of the processing target object and a second supply unit configured to supply a gas toward outer region than the central region; a second processing gas containing a hydrocarbon gas and a fluorocarbon gas is supplied from either one of the first supply unit and the second supply unit; and the first processing gas and the second processing gas are excited.
摘要翻译：蚀刻多层膜的蚀刻方法包括通过在等离子体处理装置的处理容器内产生等离子体来蚀刻多层膜。在多层膜的蚀刻中，从第一供给单元供给包含氢气，溴化氢气体，含氟气体，烃气体，氢氟烃气体和碳氟化合物气体的第一处理气体，气体朝向处理对象物的中心区域;第二供给单元，被配置为向中心区域的外部区域供给气体; 从第一供应单元和第二供应单元中的任一个供应包含烃气体和碳氟化合物气体的第二处理气体; 并且第一处理气体和第二处理气体被激发。

88. 发明授权

US09431414B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09431414B2
公开(公告)日：2016-08-30
申请号：US14517025
申请日：2014-10-17
申请人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
发明人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11565 , H01L27/1158 , H01L29/66833 , H01L29/7926
摘要： Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.
摘要翻译：非易失性存储器件包括至少四个圆柱形沟道区域，当从垂直于衬底表面的垂直方向观察时，至少四个圆柱形沟道区域从位于至少一个菱形晶体的相应顶点处的衬底的部分垂直延伸。电荷存储层（例如，ONO层）设置在每个圆柱形沟道区的外侧壁上。此外，为了实现高度的集成，提供了多个垂直堆叠的栅电极，其在每个圆柱形沟道区域附近延伸。

89. 发明申请

US20160218109A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20160218109A1
公开(公告)日：2016-07-28
申请号：US15092774
申请日：2016-04-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroshi SHINOHARA , Atsuhiro Sato , Keisuke Yonehama , Yasuyuki Baba , Toshifumi Minami , Hiroyuki Maeda , Shinji Saito , Hideyuki Kamata
IPC分类号： H01L27/115 , H01L23/528 , H01L23/522
CPC分类号： H01L27/1158 , H01L21/02164 , H01L21/0217 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.
摘要翻译：根据一个实施例，半导体存储器件包括：半导体衬底; 半导体衬底上的第一半导体柱; 包括第一部分和第二部分的第一绝缘层，所述第一部分与所述半导体衬底接触并且所述第一半导体柱的底部和所述第二部分覆盖所述第一半导体柱的一侧; 导电层和第二绝缘层，层叠在半导体衬底上并覆盖第一绝缘层的第二部分; 第一半导体柱上的第一插头; 以及第一插头上的互连。

90. 发明申请

US20160071793A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20160071793A1
公开(公告)日：2016-03-10
申请号：US14643585
申请日：2015-03-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroshi SHINOHARA , Atsuhiro SATO , Keisuke YONEHAMA , Yasuyuki BABA , Toshifumi MINAMI , Hiroyuki MAEDA , Shinji SAITO , Hideyuki KAMATA
IPC分类号： H01L23/528 , H01L21/02 , H01L21/768 , H01L27/115 , H01L23/535
CPC分类号： H01L27/1158 , H01L21/02164 , H01L21/0217 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

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