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81. 发明申请

US20140197482A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20140197482A1
公开(公告)日：2014-07-17
申请号：US14183097
申请日：2014-02-18
申请人： Noriaki MIKASA
发明人： Noriaki MIKASA
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.
摘要翻译：半导体器件包括具有第一栅极沟槽的半导体衬底，第一栅极沟槽具有彼此面对的第一和第二侧壁。第一栅极绝缘膜覆盖第一和第二侧壁。第一栅电极设置在第一栅极绝缘膜上和第一栅极沟槽的下部。第一掩埋绝缘膜将第一栅极沟槽覆盖并覆盖第一栅电极。第一扩散区域与第一栅极绝缘膜的第一上部相邻。第一上部位于第一门槽的第一侧壁的上部。第二扩散区域与第一栅极沟槽的第二侧壁的上部接触。

82. 发明申请

US20140187038A1 HIGH TEMPERATURE TUNGSTEN METALLIZATION PROCESS 有权
标题翻译：高温钨钢冶金工艺
公开(公告)号：US20140187038A1
公开(公告)日：2014-07-03
申请号：US14145434
申请日：2013-12-31
申请人： Applied Materials, Inc.
发明人： Joshua COLLINS , Murali K. NARASIMHAN , Jingjing LIU , Sang-Hyeob LEE , Kai WU , Avgerinos V. GELATOS
IPC分类号： H01L21/768
CPC分类号： H01L21/76876 , H01L21/743 , H01L21/76814 , H01L21/76841 , H01L21/76843 , H01L21/76861 , H01L21/76864 , H01L21/76877 , H01L23/53266 , H01L27/10885 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide an improved process for depositing tungsten-containing materials. In one embodiment, the method for forming a tungsten-containing material on a substrate includes forming an adhesion layer containing titanium nitride on a dielectric layer disposed on a substrate, forming a tungsten nitride intermediate layer on the adhesion layer, wherein the tungsten nitride intermediate layer contains tungsten nitride and carbon. The method further includes forming a tungsten barrier layer (e.g., tungsten or tungsten-carbon material) from the tungsten nitride intermediate layer by thermal decomposition during a thermal annealing process (e.g., temperature from about 700° C. to less than 1,000° C.). Subsequently, the method includes optionally forming a nucleation layer on the tungsten barrier layer, optionally exposing the tungsten barrier layer and/or the nucleation layer to a reducing agent during soak processes, and forming a tungsten bulk layer on or over the tungsten barrier layer and/or the nucleation layer.
摘要翻译：本发明的实施方案提供了一种用于沉积含钨材料的改进方法。在一个实施例中，在基板上形成含钨材料的方法包括在设置在基板上的电介质层上形成含有氮化钛的粘合层，在粘合层上形成氮化钨中间层，其中氮化钨中间层含有氮化钨和碳。该方法还包括在热退火过程中（例如，从约700℃至小于1000℃的温度）通过热分解从氮化钨中间层形成钨阻挡层（例如，钨或钨 - 碳材料））。随后，该方法包括任选地在钨阻挡层上形成成核层，任选地在浸泡过程期间将钨阻挡层和/或成核层暴露于还原剂，以及在钨阻挡层上或之上形成钨体层，以及 /或成核层。

83. 发明申请

US20140159194A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140159194A1
公开(公告)日：2014-06-12
申请号：US14103195
申请日：2013-12-11
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Bo-young SONG , Cheol-ju YUN , Seung-hee KO
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/764 , H01L27/10811 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10891 , H01L28/90
摘要： A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.
摘要翻译：半导体器件包括具有由器件隔离区限定的多个有源区，多个有源区上的多个导电图案，每个导电图案具有侧壁的基板，面向所述多个有源区的侧壁的导电线在有源区上具有空气间隔物的导电图案，导电线在第一方向上延伸，以及覆盖空气间隔物和导电图案之间的导电图案的侧壁的第一绝缘膜。靠近基板的第一绝缘膜的下部向空气间隔件突出。

84. 发明申请

US20140159148A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140159148A1
公开(公告)日：2014-06-12
申请号：US14097937
申请日：2013-12-05
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Woo Chung , Jiyoung Kim , Yoosang Hwang
IPC分类号： H01L29/78
CPC分类号： H01L27/10814 , H01L27/10876 , H01L27/10891 , H01L27/10894
摘要： A method of manufacturing a semiconductor device includes forming device isolation layer in a substrate to define active regions of which each has first regions and a second region between the first regions, forming a first trench and a pair of second trenches in the substrate, and forming gates in the second trenches, respectively. The first trench extends in a first direction and crosses the active regions and the device isolation layer. The second trenches are connected to a bottom of the first trench and extend in the first direction at both sides of the second regions.
摘要翻译：一种制造半导体器件的方法包括在衬底中形成器件隔离层，以限定其中各具有第一区域的有源区和在第一区之间的第二区，在衬底中形成第一沟槽和一对第二沟槽，分别在第二壕沟的大门。第一沟槽沿第一方向延伸并与有源区和器件隔离层交叉。第二沟槽连接到第一沟槽的底部并且在第二区域的两侧沿第一方向延伸。

85. 发明申请

US20140124844A1 SEMICONDUCTOR LAYOUT STRUCTURE 有权
标题翻译：半导体布局结构
公开(公告)号：US20140124844A1
公开(公告)日：2014-05-08
申请号：US13831907
申请日：2013-03-15
申请人： INOTERA MEMORIES, INC.
发明人： Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L27/07 , H01L29/78
CPC分类号： H01L27/10882 , H01L27/0207 , H01L27/10885 , H01L27/10891 , H01L45/122
摘要： A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction.
摘要翻译：半导体布局结构包括多个有源块，它们设置在彼此平行并且沿着第一方向延伸的基板上，多个第一浅沟槽隔离件设置在基板上，彼此平行并分别设置在多个有源块以及多个第二浅沟槽隔离件，其被布置在基板上，切割多个有源块并且沿第二方向延伸。第一方向具有与第二方向大约1度至大约53度的角度。

86. 发明申请

US20140112050A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140112050A1
公开(公告)日：2014-04-24
申请号：US14051841
申请日：2013-10-11
申请人： Jemin PARK
发明人： Jemin PARK
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , H01L27/10882 , H01L27/10885 , H01L27/10888 , H01L27/10891
摘要： A semiconductor device includes a plurality of word lines; a plurality of bit lines; and a plurality of bit line node contacts. The plurality of word lines extend in a first direction in or on a substrate. The plurality of bit lines crosses over the plurality of word lines. Each of the plurality of bit line node contacts connects a corresponding bit line to the substrate, and each of the plurality of bit line node contacts has a width substantially equal to a width of the corresponding bit line.
摘要翻译：半导体器件包括多个字线; 多个位线; 和多个位线节点接点。多个字线在衬底中或衬底上沿第一方向延伸。多个位线在多个字线上交叉。多个位线节点触点中的每一个将对应的位线连接到衬底，并且多个位线节点触点中的每一个具有基本上等于对应位线的宽度的宽度。

87. 发明申请

US20140094026A1 METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES 有权
公开(公告)号：US20140094026A1
公开(公告)日：2014-04-03
申请号：US14096052
申请日：2013-12-04
申请人： MICRON TECHNOLOGY, INC.
发明人： Gurtej Sandhu , Scott Sills
IPC分类号： H01L21/285 , H01L21/768 , H01L21/28
CPC分类号： H01L27/10885 , H01L21/28008 , H01L21/28035 , H01L21/28518 , H01L21/3081 , H01L21/32139 , H01L21/76877 , H01L21/76895 , H01L21/823871 , H01L23/528 , H01L23/5283 , H01L27/10888 , H01L27/10891 , H01L2224/06138 , H01L2924/12044
摘要： An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

88. 发明申请

US20140042548A1 DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF 审中-公开
标题翻译：具有BURIED字线和其制造的DRAM结构及其结构和制造
公开(公告)号：US20140042548A1
公开(公告)日：2014-02-13
申请号：US14047018
申请日：2013-10-07
申请人： NANYA TECHNOLOGY CORPORATION
发明人： Hao-Chieh Liu , Lars Heineck , Ping-Chieh Chiang
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines.
摘要翻译：描述了具有埋置字线的DRAM结构，包括半导体衬底，埋在衬底中并由第一栅极电介质层与其分离的单元字线，以及掩埋在衬底中的隔离字线，并与第二栅极隔离的隔离字线栅介质层。单元字线的顶表面和隔离字线的顶表面低于衬底的顶表面。隔离字线的底面低于单元字线的底面。

89. 发明授权

US08629051B2 Method for providing electrical connections to spaced conductive lines 有权
公开(公告)号：US08629051B2
公开(公告)日：2014-01-14
申请号：US13751781
申请日：2013-01-28
申请人： Micron Technology, Inc.
发明人： Gurtej Sandhu , Scott Sills
IPC分类号： H01L21/44
CPC分类号： H01L27/10885 , H01L21/28008 , H01L21/28035 , H01L21/28518 , H01L21/3081 , H01L21/32139 , H01L21/76877 , H01L21/76895 , H01L21/823871 , H01L23/528 , H01L23/5283 , H01L27/10888 , H01L27/10891 , H01L2224/06138 , H01L2924/12044
摘要： An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

90. 发明授权

US08624350B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08624350B2
公开(公告)日：2014-01-07
申请号：US13243386
申请日：2011-09-23
申请人： Do Hyung Kim , Young Man Cho
发明人： Do Hyung Kim , Young Man Cho
IPC分类号： H01L21/70
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L29/4236
摘要： The invention relates to a semiconductor device, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance. A semiconductor device according to the invention comprises: first and second active regions formed in a substrate, the first and second active being adjacent to each other, each of the first and second active regions including a bit-line contact region and a storage node contact region and a device isolation structure; a word line provided within a trench formed in the substrate; first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and a bit line formed within the bit-line groove.
摘要翻译：本发明涉及一种半导体器件，其中存储节点接触孔较大以解决在用小CD刻蚀存储节点接触孔期间引起的任何问题，形成了降低插头电阻的着陆插头。根据本发明的半导体器件包括：形成在衬底中的第一和第二有源区，第一和第二有源层彼此相邻，第一和第二有源区域中的每一个包括位线接触区域和存储节点接触区域和器件隔离结构; 设置在形成在所述基板中的沟槽内的字线; 分别分配给第一和第二有源区域的第一和第二存储节点接触插塞，第一和第二存储节点接触插塞通过位线槽相互分离; 以及形成在位线槽内的位线。

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