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81. 发明申请

US20050095872A1 HDP PROCESS FOR HIGH ASPECT RATIO GAP FILLING 失效
标题翻译：用于高比例差压填充的HDP工艺
公开(公告)号：US20050095872A1
公开(公告)日：2005-05-05
申请号：US10605857
申请日：2003-10-31
申请人： Michael Belyansky , Patricia Argandona , Gregory DiBello , Andreas Knorr , Daewon Yang
发明人： Michael Belyansky , Patricia Argandona , Gregory DiBello , Andreas Knorr , Daewon Yang
IPC分类号： H01L21/314 , H01L21/316 , H01L21/318 , H01L21/762 , H01L21/8242 , H01L21/31 , H01L21/76
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/31608 , H01L21/31625 , H01L21/31629 , H01L21/3185 , H01L21/76224 , H01L27/10844
摘要： An HDP process for high aspect ratio gap filling comprises contacting a semiconductor substrate with an oxide precursor under high density plasma conditions at a first pressure less than about 10 millitorr, wherein said gaps are partially filled with oxide; and further contacting the substrate with an oxide precursor under high density plasma conditions at a second pressure greater than about 10 millitorr, wherein said gaps are further filled with oxide.
摘要翻译：用于高纵横比间隙填充的HDP工艺包括在高密度等离子体条件下以低于约10毫托的第一压力使半导体衬底与氧化物前体接触，其中所述间隙部分地填充有氧化物; 并且在高密度等离子体条件下，在大于约10毫托的第二压力下进一步使基底与氧化物前体接触，其中所述间隙进一步用氧化物填充。

82. 发明申请

US20050064207A1 System and method for forming multi-component dielectric films 失效
公开(公告)号：US20050064207A1
公开(公告)日：2005-03-24
申请号：US10829781
申请日：2004-04-21
申请人： Yoshihide Senzaki , Seung Park
发明人： Yoshihide Senzaki , Seung Park
IPC分类号： C23C16/02 , C23C16/30 , C23C16/40 , C23C16/44 , C23C16/455 , H01L21/314 , H01L21/316 , B32B9/04 , C23C16/00
CPC分类号： C23C16/45531 , C23C16/029 , C23C16/308 , C23C16/401 , H01L21/3141 , H01L21/3142 , H01L21/3143 , H01L21/3145 , H01L21/31608 , H01L21/31612 , H01L21/31645
摘要： The present invention provides systems and methods for mixing precursors such that a mixture of precursors are present together in a chamber during a single pulse step in an atomic layer deposition (ALD) process to form a multi-component film. The precursors are comprised of at least one different chemical component, and such different components will form a mono-layer to produce a multi-component film. In a further aspect of the present invention, a dielectric film having a composition gradient is provided.

83. 发明授权

US06858697B2 Stabilizers to inhibit the polymerization of substituted cyclotetrasiloxane 有权
标题翻译：抑制取代环四硅氧烷聚合的稳定剂
公开(公告)号：US06858697B2
公开(公告)日：2005-02-22
申请号：US10029892
申请日：2001-12-21
申请人： Steven Gerard Mayorga , Manchao Xiao , Thomas Richard Gaffney
发明人： Steven Gerard Mayorga , Manchao Xiao , Thomas Richard Gaffney
IPC分类号： C07F7/20 , C07F7/21 , C09D4/00 , C23C16/40 , C23C16/42 , H01L21/316
CPC分类号： C23C16/401 , C07F7/20 , C07F7/21 , C09D4/00 , H01L21/31608 , C08G77/04
摘要： The present invention is; (a) a process for stabilizing a cyclotetrasiloxane, such as 1,3,5,7-tetramethylcyclotetrasiloxane, against polymerization used in a chemical vapor deposition process for silicon oxides in electronic material fabrication comprising providing an effective amount of a neutral to weakly acidic polymerization inhibitor to such cyclotetrasiloxane; and (b) a composition of a cyclotetrasiloxane, such as 1,3,5,7-tetramethylcyclotetrasiloxane, stabilized against polymerization used in a chemical vapor deposition process as a precursor for silicon oxides in electronic material fabrication, comprising; such cyclotetrasiloxane and a neutral to weakly acidic polymerization inhibitor. A free radical scavenger can also be included in the process and composition.
摘要翻译：本发明是（a）用于稳定环四硅氧烷（例如1,3,5,7-四甲基环四硅氧烷）的方法，用于在用于电子材料制造中的氧化硅的化学气相沉积方法中使用的聚合，包括提供有效量的中性至弱酸性聚合这种环四硅氧烷的抑制剂; 和（b）在电子材料制造中作为氧化硅前体的化学气相沉积方法中使用的稳定的聚合的1,3,5,7-四甲基环四硅氧烷的环四硅氧烷的组合物，包括：这种环四硅氧烷和中性至弱酸性聚合抑制剂。自由基清除剂也可以包含在该过程和组合物中。

84. 发明申请

US20050035379A1 Semiconductor device structured to prevent oxide damage during HDP CVD 审中-公开
标题翻译：构造为防止HDP CVD期间的氧化物损伤的半导体器件
公开(公告)号：US20050035379A1
公开(公告)日：2005-02-17
申请号：US10942786
申请日：2004-09-17
申请人： Minoru Saito
发明人： Minoru Saito
IPC分类号： H01L21/31 , H01L21/316 , H01L21/318 , H01L21/336 , H01L21/8234 , H01L23/31 , H01L23/52 , H01L23/532 , H01L23/58 , H01L29/94 , H01L31/113
CPC分类号： H01L23/3192 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/31608 , H01L21/31629 , H01L21/3185 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： A semiconductor device includes a patterned conductive layer on which an initial dielectric film is deposited by a non-etching deposition process. A second dielectric film is then deposited on the initial dielectric film by high-density plasma chemical vapor deposition (HDP CVD). The HDP CVD process etches the second dielectric film as it is being deposited, thereby smoothing the surface of the second dielectric film. The initial dielectric film insulates the patterned conductive layer from the plasma used in the HDP CVD process, so that plasma charge is not conducted to underlying oxide films, such as gate oxide films, and does not cause oxide damage.
摘要翻译：半导体器件包括图案化导电层，其上通过非蚀刻沉积工艺沉积初始电介质膜。然后通过高密度等离子体化学气相沉积（HDP CVD）将第二电介质膜沉积在初始电介质膜上。 HDP CVD工艺在其被沉积时蚀刻第二介电膜，从而平滑第二电介质膜的表面。初始电介质膜将图案化的导电层与HDP CVD工艺中使用的等离子体绝缘，使得等离子体电荷不被引导到下面的氧化膜，例如栅极氧化膜，并且不会引起氧化物损伤。

85. 发明申请

US20050032382A1 Staggered in-situ deposition and etching of a dielectric layer for HDP CVD 失效
标题翻译：用于HDP CVD的电介质层的交错原位沉积和蚀刻
公开(公告)号：US20050032382A1
公开(公告)日：2005-02-10
申请号：US10938174
申请日：2004-09-10
申请人： Kent Rossman
发明人： Kent Rossman
IPC分类号： C23C16/04 , C23C16/40 , C23C16/44 , C23C16/455 , H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/311 , H01L21/469 , H01L21/4763
CPC分类号： C23C16/45523 , C23C16/045 , C23C16/402 , C23C16/4482 , C23C16/45561 , C23C16/507 , H01J37/321 , H01J37/32302 , H01J37/32449 , H01J37/32862 , H01J37/3299 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/31051 , H01L21/31608 , H01L21/31612 , H01L21/76837
摘要： A method and apparatus for depositing a conformal dielectric layer employing a dep-etch technique features selectively reducing the flow of deposition gases into a process chamber where a substrate having a stepped surface to be covered by the conformal dielectric layer is disposed. By selectively reducing the flow of deposition gases into the process chamber, the concentration of a sputtering gas, from which a plasma is formed, in the process chamber is increased without increasing the pressure therein. It is preferred that the flow of deposition gases be periodically terminated so as to provide a sputtering gas concentration approaching 100%. In this fashion, the etch rate of a conformal dielectric layer having adequate gap-filling characteristics may be greatly increased, while allowing an increase in the deposition rate of the same.
摘要翻译：使用去蚀刻技术沉积保形介电层的方法和装置特征在于选择性地减少沉积气体流入处理室，其中设置具有被保形电介质层覆盖的台阶表面的基板。通过选择性地减少沉积气体进入处理室的流量，在处理室中从其中形成等离子体的溅射气体的浓度增加而不增加其中的压力。沉积气体的流动优选地周期性地终止，以提供接近100％的溅射气体浓度。以这种方式，可以大大增加具有足够的间隙填充特性的保形介电层的蚀刻速率，同时允许其沉积速率的增加。

86. 发明授权

US06830979B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06830979B2
公开(公告)日：2004-12-14
申请号：US10152334
申请日：2002-05-22
申请人： Yukihisa Wada
发明人： Yukihisa Wada
IPC分类号： H10L21336
CPC分类号： H01L21/823468 , H01L21/31111 , H01L21/31608 , H01L21/31625 , H01L21/3185 , H01L21/76224 , H01L28/84 , H01L28/91 , H01L29/6653
摘要： There is provided a method for fabricating a semiconductor device involving the formation of two or more oxide films having different etching properties. A multilayer-film sidewall including a first oxide film such as an NSG film, a TEOS film, or a HTO film and a second oxide film such as a BPSG film or a PSG film is formed over the side surfaces of a gate electrode. After the multilayer-film sidewall is used as an implantation mask for forming the source and drain of a MIS transistor, wet etching is performed by using an aqueous solution mixture containing a hydrofluoric acid and an inorganic acid (a hydrochloric acid, a sulfuric acid, or the like) in selectively removing the second oxide film. This increases the etching selectivity between the individual oxide films and allows the removal of only the upper-layer second oxide film.
摘要翻译：提供了一种用于制造半导体器件的方法，该半导体器件涉及形成具有不同蚀刻性能的两个或更多个氧化物膜。在栅电极的侧面上形成包括诸如NSG膜，TEOS膜或HTO膜的第一氧化物膜和诸如BPSG膜或PSG膜的第二氧化物膜的多层膜侧壁。在将多层膜侧壁用作用于形成MIS晶体管的源极和漏极的注入掩模之后，通过使用含有氢氟酸和无机酸（盐酸，硫酸，等）选择性地除去第二氧化物膜。这增加了各个氧化物膜之间的蚀刻选择性，并允许仅去除上层第二氧化物膜。

87. 发明授权

US06799303B2 Speed typing apparatus and method 有权
标题翻译：快速打字设备和方法
公开(公告)号：US06799303B2
公开(公告)日：2004-09-28
申请号：US09912509
申请日：2001-07-26
申请人： Marvin R. Blumberg
发明人： Marvin R. Blumberg
IPC分类号： G06F1721
CPC分类号： G06F3/0237 , C01P2002/82 , C01P2006/16 , C09C1/3081 , C09C1/3684 , G06F3/023 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/3105 , H01L21/31608 , H01L21/31695
摘要： A speed typing method and apparatus having multiple letters associated with each key of a keyboard. By utilizing multiple characters on each key, the number of keys would be fewer than the number of letters in the alphabet using this system. Each key on the keyboard is associated with a numerical code. The system uses the numerical code associated with a typed word to access a dictionary, table of words, or at least a beginning of words stored in memory at a memory location corresponding to the input numerical code. The system may display all of the possible words or beginnings of words available to the user in response to the input code.
摘要翻译：具有与键盘的每个键相关联的多个字母的速度分类方法和装置。通过在每个键上使用多个字符，键的数量将少于使用该系统的字母表中的字母数。键盘上的每个键都与数字代码相关联。该系统使用与打字字相关联的数字代码来访问字典，单词表，或存储在与输入数字代码对应的存储器位置的存储器中的至少一个字的开头。系统可以响应于输入代码显示用户可用的所有可能的单词或开始的单词。

88. 发明授权

US06762128B2 Apparatus and method for manufacturing a semiconductor circuit 有权
标题翻译：用于制造半导体电路的装置和方法
公开(公告)号：US06762128B2
公开(公告)日：2004-07-13
申请号：US10177915
申请日：2002-06-20
申请人： Paul A. Bernkopf , Frederick T. Brady , Nadim Haddad
发明人： Paul A. Bernkopf , Frederick T. Brady , Nadim Haddad
IPC分类号： H01L21302
CPC分类号： H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/31608 , H01L21/76229
摘要： A method and an apparatus for manufacturing, via a single fabrication line, circuits that are radiation tolerant and also circuits that are radiation intolerant. When production calls for radiation-tolerant circuits, low-pressure chemical vapor deposition is advantageously used to deposit an electrically-insulating material, such as silicon dioxide, in trenches to provide electrical isolation between adjacent semiconductor devices. When production requires radiation-intolerant circuits, as may be required for export, then the trenches are filled via a procedure that deposits an electrically-insulating material that, on exposure to ionizing radiation, generates a suitably large amount of “positive charge traps.” One procedure suitable for creating such positive charge traps is high-density plasma chemical vapor deposition (HDPCVD).
摘要翻译：一种用于通过单个制造线制造耐辐射电路以及辐射不耐受的电路的方法和装置。当生产要求耐辐射电路时，低压化学气相沉积有利地用于在沟槽中沉积诸如二氧化硅的电绝缘材料，以在相邻的半导体器件之间提供电隔离。当生产需要耐辐射电路时，可能需要输出电路，然后通过沉积电绝缘材料的程序来填充沟槽，这些电绝缘材料在暴露于电离辐射时产生适当大量的“正电荷陷阱”。适用于产生这种正电荷陷阱的一种方法是高密度等离子体化学气相沉积（HDPCVD）。

89. 发明授权

US06753258B1 Integration scheme for dual damascene structure 失效
标题翻译：双镶嵌结构的整合方案
公开(公告)号：US06753258B1
公开(公告)日：2004-06-22
申请号：US09706298
申请日：2000-11-03
申请人： Frederic Gaillard , Li-Qun Xia , Ellie Yieh , Paul Fisher , Margaret Gotuaco
发明人： Frederic Gaillard , Li-Qun Xia , Ellie Yieh , Paul Fisher , Margaret Gotuaco
IPC分类号： H01L21302
CPC分类号： H01L21/76801 , H01L21/31608 , H01L21/76807 , H01L21/76834 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for processing a substrate to form a feature in low k dielectric materials. One aspect of the invention provides a method for processing a substrate including forming a feature definition in a dielectric material deposited on a surface of a substrate, depositing one or more conductive materials to fill at least a portion of the feature definition, planarizing the substrate surface to expose the dielectric material, removing at least a portion of the dielectric material, and depositing a low k dielectric material.
摘要翻译：一种用于处理基底以在低k电介质材料中形成特征的方法和装置。本发明的一个方面提供一种处理衬底的方法，包括在沉积在衬底的表面上的电介质材料中形成特征定义，沉积一种或多种导电材料以填充特征定义的至少一部分，平坦化衬底表面以暴露电介质材料，去除介电材料的至少一部分，以及沉积低k电介质材料。

90. 发明申请

US20040054114A1 Stabilizers to inhibit the polymerization of substituted cyclotetrasiloxane 有权
标题翻译：抑制取代环四硅氧烷聚合的稳定剂
公开(公告)号：US20040054114A1
公开(公告)日：2004-03-18
申请号：US10602279
申请日：2003-06-23
发明人： Steven Gerard Mayorga , Manchao Xiao , Thomas Richard Gaffney , Robert George Syvret
IPC分类号： C08G077/06
CPC分类号： C23C16/401 , C07F7/20 , C07F7/21 , C08K5/13 , C09D4/00 , H01L21/02164 , H01L21/02271 , H01L21/31608 , C08G77/04
摘要： The present invention is; (a) a process for stabilizing a cyclotetrasiloxane, such as 1,3,5,7-tetramethylcyclotetrasiloxane, against polymerization used in a chemical vapor deposition process for silicon oxides in electronic material fabrication comprising providing an effective amount of a free radical scavenger polymerization inhibitor to such cyclotetrasiloxane; and (b) a composition of a cyclotetrasiloxane, such as 1,3,5,7-tetramethylcyclotetrasiloxane, stabilized against polymerization used in a chemical vapor deposition process as a precursor for silicon oxides in electronic material fabrication, comprising; such cyclotetrasiloxane and a free radical scavenger polymerization inhibitor.
摘要翻译：本发明是（a）用于稳定环四硅氧烷（例如1,3,5,7-四甲基环四硅氧烷）的方法，用于电子材料制造中用于氧化硅的化学气相沉积方法中的聚合，包括提供有效量的自由基清除剂聚合抑制剂到这种环四硅氧烷; 和（b）在电子材料制造中作为氧化硅前体的化学气相沉积方法中使用的稳定的聚合的1,3,5,7-四甲基环四硅氧烷的环四硅氧烷的组合物，包括：这种环四硅氧烷和自由基清除剂聚合抑制剂。

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