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81. 发明授权

US5434591A Scrolling method and apparatus in which data being displayed is altered during scrolling 失效
标题翻译：滚动方法和装置，其中显示的数据在滚动期间被改变
公开(公告)号：US5434591A
公开(公告)日：1995-07-18
申请号：US570299
申请日：1990-08-20
申请人： Masahiro Goto , Seiichi Shinno
发明人： Masahiro Goto , Seiichi Shinno
IPC分类号： G06F3/14 , G06F3/048 , G06T11/60 , G09B29/00 , G09G5/34 , G09G5/36 , G09G5/38 , G09G5/395 , G09G5/397 , G09G5/399 , G09G1/06
CPC分类号： G09G5/397 , G09G5/346 , G09G5/395 , G09G2340/12
摘要： In a scrolling of a display of graphic data in response to an operator command, a characteristic of the data is altered, according to the speed of the scrolling, to facilitate the viewing of the data as the data is scrolled. In one case, a selected part of the data is omitted from the display during scrolling so that a reduced amount of data is displayed, the amount of reduction in displayed data being proportional to the scrolling period. As another possibility, or in addition thereto, the magnification of the data being displayed is varied with variation in the scrolling speed. The magnification can be controlled so that the apparent speed of the movement of the displayed data at a given scrolling speed is maintained substantially constant as the scrolling period is varied from the given scrolling speed. A further possibility is to alter the data by emphasizing a portion of the data in the display in a selected manner. Thus, even when the scrolling speed is set at the maximum speed which the human eye can follow, the displayed data can be viewed easily, and the retrieval operation there by can be facilitated.
摘要翻译：在响应于操作者命令的图形数据的显示的滚动中，根据滚动的速度来改变数据的特性，以便于在数据滚动时观看数据。在一种情况下，在滚动期间从显示器中省略选择的部分数据，从而显示减少的数据量，显示数据的减少量与滚动周期成正比。作为另一种可能性，或者除此之外，正在显示的数据的放大率随着滚动速度的变化而变化。可以控制倍率，使得随着滚动周期从给定的滚动速度变化，以给定的滚动速度显示的数据的运动的表观速度保持基本上恒定。另一种可能性是通过以选定的方式强调显示器中的一部分数据来改变数据。因此，即使将滚动速度设定为人眼可以追随的最大速度，也能够容易地观看所显示的数据，并且能够容易地进行检索操作。

82. 发明授权

US5250928A Graphics decoder 失效
标题翻译：图形解码器
公开(公告)号：US5250928A
公开(公告)日：1993-10-05
申请号：US903165
申请日：1992-06-24
申请人： Shinji Kuriki
发明人： Shinji Kuriki
IPC分类号： G06F3/153 , G09G5/06 , G09G5/34 , G09G5/36 , H04N9/74 , H04N9/82 , G09G1/28
CPC分类号： H04N9/8244 , G06F3/153 , G09G5/06 , G09G5/346
摘要： A graphics decoder which stores color number data of each pixel of the display screen, which is acquired from a subcode signal, sequentially reads out the color number data to produce a graphics RGB signal referring to a color look-up table, and supplies the graphics RGB signal to a CRT display. When a graphics command acquired from the subcode signal is a screen-scroll command, scroll data is obtained from pointer data included in that scroll command, and that scroll data is output at a timing synchronous with a horizontal sync signal or vertical sync signal to set the read address of the display memory. When the graphics command is a color look-up table write command, the color look-up table is updated at a timing synchronous with the first horizontal sync signal or vertical sync signal after the generation of that write command.

83. 发明授权

US5089811A Advanced video processor having a color palette 失效
标题翻译：具有调色板的高级视频处理器
公开(公告)号：US5089811A
公开(公告)日：1992-02-18
申请号：US455869
申请日：1989-12-18
申请人： Jerald G. Leach
发明人： Jerald G. Leach
IPC分类号： G09G5/34
CPC分类号： G09G5/346
摘要： An advanced video processor generates displays for displaying of either graphics or text information via a display monitor or a TV set operating as a monitor. A color palette is included in the advanced video processor for programming of the color of the display. The color palette provides 512 color selections, any sixteen of which may be displayed at once.
摘要翻译：高级视频处理器通过显示监视器或作为监视器操作的电视机产生用于显示图形或文本信息的显示器。高级视频处理器中包含一个调色板，用于编程显示器的颜色。调色板提供512种颜色选择，其中十六种可以一次显示。

84. 发明授权

US4851834A Multiport memory and source arrangement for pixel information 失效
标题翻译：用于像素信息的多端口存储器和源排列
公开(公告)号：US4851834A
公开(公告)日：1989-07-25
申请号：US68728
申请日：1987-06-29
申请人： Thomas C. Stockebrand , Joel D. Kaufman , Earle R. Vicery, III
发明人： Thomas C. Stockebrand , Joel D. Kaufman , Earle R. Vicery, III
IPC分类号： G09G5/34 , G09G5/36 , G09G5/39 , G09G5/393
CPC分类号： G09G5/393 , G09G5/346 , G09G5/363 , G09G2360/127
摘要： The present system includes, in a preferred embodiment, a plurality of bit map memory units which together define a large bit map memory. For each bit map memory unit there is also included a mask means and four extended shift registers. The shift registers can be loaded in parallel with pixel information through bidirectional data transmission channels which include bidirectional mask means. The pixel information can be routed through said bidirectional mask means to different address locations, or to the same address location, with certain of the pixel bits removed by the mask means. The shift registers have both serial and parallel input and output means and are clocked at different speeds to accommodate different peripherals. At least a first shift register is designed to be serially read out at a relatively high rate which can be advantageously used by a video display device or the like. Information signals from the other shift registers are transferred at high speed (in parallel) into and out of the large bit map memory to said first shift register whereby pixel information signals are settled down before being routed from said first shift register. The bidirectional mask means and the bidirectional data transmission channels along with the multiplicity of shift registers permit the present system to handle many varied operations which operate at different speeds, etc.
摘要翻译：在优选实施例中，本系统包括多个位图存储单元，它们共同限定大位图存储器。对于每个位图存储器单元，还包括掩模装置和四个扩展移位寄存器。移位寄存器可以通过包括双向屏蔽装置的双向数据传输通道与像素信息并行加载。像素信息可以通过所述双向掩码装置被路由到不同的地址位置，或者通过掩码装置去除某些像素比特到相同的地址位置。移位寄存器具有串行和并行输入和输出装置，并以不同的速度计时以适应不同的外设。至少第一移位寄存器被设计为以相对较高的速率串行读出，这可以有利于视频显示设备等使用。来自其他移位寄存器的信息信号以高速（并行）传送到大位图存储器中并输出到所述第一移位寄存器，由此像素信息信号在从所述第一移位寄存器路由之前被稳定下来。双向屏蔽装置和双向数据传输通道以及多个移位寄存器允许本系统处理以不同速度等操作的许多不同的操作。

85. 发明授权

US4769637A Video display control circuit arrangement 失效
标题翻译：视频显示控制电路布置
公开(公告)号：US4769637A
公开(公告)日：1988-09-06
申请号：US802226
申请日：1985-11-26
申请人： Ned C. Forrester , Robert C. Rose , Thomas C. Furlong
发明人： Ned C. Forrester , Robert C. Rose , Thomas C. Furlong
IPC分类号： G09G5/00 , G06F3/153 , G09G5/14 , G09G5/34 , G09G1/16
CPC分类号： G09G5/346
摘要： The present circuit arrangement is principally directed to scrolling of a region or regions on a video display and includes a bit map memory, at least one address generation and control signal circuitry chip, one or more data signal path circuitry chips, timing circuitry and logic circuitry interconnecting the foregoing various sections of circuitry. The present arrangement functions to refresh, scroll and update during each horizontal scan, in response to a plurality of timing cycles, with every other cycle being a refresh cycle and the intervening cycles being either scroll or update cycles. During a refresh cycle there is a burst of signals read from memory and transmitted to a shift register feeding the video screen to effect refreshing a section of the screen. At the same time those signals are used to refresh the memory. During the alternate cycles (between refresh cycles) there may be a burst of signals from the signal path circuitry chip to write information into the bit map memory at some new address to effect scrolling. Instead of performing scrolling in the alternate cycles, information may be erased from a region. In the alternative there may be a burst of signals from an information source transmitted to the bit map memory to effect updating (i.e. writing new data information into the memory). The foregoing arrangement permits the entire bit map memory to be rewritten during the period required for one vertical scan of the video display device which in turn enables the system to provide rapid smooth scrolling and continued sequential addressing of the memory.
摘要翻译：本电路装置主要针对视频显示器上的区域或区域的滚动，并且包括位图存储器，至少一个地址生成和控制信号电路芯片，一个或多个数据信号路径电路芯片，定时电路和逻辑电路互连电路的前述各个部分。本布置用于响应于多个定时周期在每个水平扫描期间刷新，滚动和更新，其中每隔一个周期是刷新周期，并且中间周期是滚动或更新周期。在刷新周期期间，存储从存储器读取的信号的一串信号，并发送到移位寄存器，该移位寄存器馈送视频屏幕以实现刷新屏幕的一部分。同时，这些信号用于刷新内存。在替代周期期间（在刷新周期之间），可能存在来自信号路径电路芯片的信号脉冲串，以在某些新地址将信息写入位图存储器以实现滚动。代替在替代周期中执行滚动，可以从区域中擦除信息。在替代方案中，可能存在来自发送到位图存储器的信息源的信号突发以实现更新（即，将新的数据信息写入存储器）。上述布置允许在视频显示设备的一次垂直扫描所需的周期期间重写整个位图存储器，这又使得系统能够提供快速平滑滚动和继续顺序寻址存储器。

86. 发明授权

US4737778A Video display controller 失效
标题翻译：视频显示控制器
公开(公告)号：US4737778A
公开(公告)日：1988-04-12
申请号：US736827
申请日：1985-05-22
申请人： Kazuhiko Nishi , Takatoshi Ishii , Ryozo Yamashita , Shigemitsu Yamaoka , Takatoshi Okumura
发明人： Kazuhiko Nishi , Takatoshi Ishii , Ryozo Yamashita , Shigemitsu Yamaoka , Takatoshi Okumura
IPC分类号： G06F3/153 , G09G5/18 , G09G5/34 , G09G1/16
CPC分类号： G09G5/346
摘要： There is provided a video display controller which can vertically and horizontally shift a whole video image displayed on a screen of a video display unit. The video display controller comprises an image data read circuit which reads the image data from a video RAM, a register into which data representative of amount of shift of the video image is stored by a central processing unit, and a first counter which cyclicly counts a clock signal. An adder adds the data contained in the register and a count output of the first counter, and at a timing determined by this addition result a predetermined value is preset into a second counter. This second counter counts the clock signal from the predetermined value, and the image data read by the image data read circuit is outputted to the video display unit at a timing in accordance with a count output of this second counter. The register, first counter, adder and second counter are provided in each of vertical and horizontal scanning control circuits.
摘要翻译：提供了一种视频显示控制器，其可以垂直和水平地移动显示在视频显示单元的屏幕上的整个视频图像。视频显示控制器包括从视频RAM读取图像数据的图像数据读取电路，由中央处理单元存储表示视频图像的移位量的数据的寄存器和循环计数视频图像的第一计数器时钟信号。加法器将包含在寄存器中的数据和第一计数器的计数输出相加，并且在由该相加结果确定的定时将预定值预设为第二计数器。该第二计数器从预定值对时钟信号进行计数，并且由图像数据读取电路读取的图像数据根据该第二计数器的计数输出在定时输出到视频显示单元。在每个垂直扫描控制电路和水平扫描控制电路中都设置寄存器，第一计数器，加法器和第二计数器。

87. 发明授权

US4706076A Apparatus for displaying images defined by a plurality of lines of data 失效
标题翻译：用于显示由多条数据线定义的图像的装置
公开(公告)号：US4706076A
公开(公告)日：1987-11-10
申请号：US651318
申请日：1984-09-17
申请人： Loriano Racchini
发明人： Loriano Racchini
IPC分类号： G09G5/00 , G06F3/14 , G09G5/30 , G09G5/34 , G09G1/16
CPC分类号： G09G5/343 , G09G5/30 , G09G5/346
摘要： Text is displayed on a VDU (23) using a character generator (26) and a generator (27) for attributes such as underline, enhanced brightness and so on. The codes for the generators are stored in a page store (29). Two auxiliary memories (35 and 36) are used to store address pointers. These memories are used in alternate raster scans to control the display, the unused memory being updated for the next raster scan. Each address pointer comprises an entry for every VDU scanning line and determines which dot video line signal will be used in that scanning line by specifying the data row address in the page memory (29) and the dot matrix row number to be used by the generators (26 and 27). Such address pointers enable complete control over the display for the purpose of defining windows, scrolling the display smoothly and slowly at the rate of one scanning line per frame and smooth expansion of a strip on the display by dulplication of lines. A CPU 10 effects the control by determining the address pointers written into the auxiliary memories. For graphics display, the address pointers store for each scanning line the number of the bit line to be used in creating the image.
摘要翻译：使用字符发生器（26）和发生器（27）在VDU（23）上显示文本，用于诸如下划线，增强亮度等属性。生成器的代码存储在页面存储器（29）中。两个辅助存储器（35和36）用于存储地址指针。这些存储器用于替代光栅扫描以控制显示，未使用的存储器正在为下一次光栅扫描进行更新。每个地址指针包括用于每个VDU扫描行的条目，并且通过指定页存储器（29）中的数据行地址和要由发生器使用的点阵行数来确定将在该扫描行中使用哪个点视频行信号（26和27）。这样的地址指针能够完全控制显示器，以便定义窗口，以每帧一条扫描线的速度平滑地和缓慢地滚动显示器，并且通过线路通过显示器上的条带的平滑展开。 CPU10通过确定写入辅助存储器的地址指针来实现控制。对于图形显示，地址指针存储每条扫描行用于创建图像的位线数。

88. 发明授权

US4653012A Display systems 失效
标题翻译：显示系统
公开(公告)号：US4653012A
公开(公告)日：1987-03-24
申请号：US640970
申请日：1984-08-15
申请人： Edward P. Duffy , Geoffrey B. Craggs , David McGlade
发明人： Edward P. Duffy , Geoffrey B. Craggs , David McGlade
IPC分类号： G06T17/00 , G09B29/10 , G09G5/34 , G06F15/50
CPC分类号： G09B29/106 , G06T17/00 , G09G5/346
摘要： A display system including a display device, a storage means having an array of storage locations each location being adapted to contain data representing a visual parameter of a different pixel of a picture to be displayed, and signal generating means for causing the display device to use the data to display a picture. the storage means is adapted to store data relating to a picture of a larger area than the picture displayed at any one time, the generating means incorporating means for altering the locations in the storage means which are addressed to produce the picture displayed in dependence on the required portion of the larger area picture which it is required to display.
摘要翻译：一种显示系统，包括显示装置，具有存储位置阵列的存储装置，每个位置适于包含表示要显示的图像的不同像素的视觉参数的数据;以及信号生成装置，用于使显示装置使用数据显示图片。存储装置适于存储与在任何一个时间显示的图像相比更大区域的图像的数据，所述生成装置包括用于改变存储装置中的位置的装置，其被寻址以产生依赖于所显示的图像需要显示的较大区域图片的所需部分。

89. 发明授权

US4611202A Split screen smooth scrolling arrangement 失效
标题翻译：拆分屏幕平滑滚动排列
公开(公告)号：US4611202A
公开(公告)日：1986-09-09
申请号：US543108
申请日：1983-10-18
申请人： Robert S. DiNitto , Thomas C. Porcher , John W. Eng
发明人： Robert S. DiNitto , Thomas C. Porcher , John W. Eng
IPC分类号： G06F3/048 , G06F3/14 , G09G5/14 , G09G5/34 , G09G1/06
CPC分类号： G09G5/346
摘要： The present invention is employed in a system which has a bit map memory connected to a CRT display device and the CRT display device can display a fixed region of information and a scrollable region of information. In a preferred embodiment, the system uses a graphic display control circuit to change starting addresses and length ending values of the fixed and scrollable regions in the bit map memory. By changing the starting address one scan line per frame, without any actual transfer of data in memory, from one location to another location, the present system effects a "smooth" scroll. The system is able to scroll upward and downward. The system uses logic circuitry to load an off screen segment of the bit map memory with additional scrollable information, so that (in an upward scroll load) as a top line of the scrollable information region is no longer displayed, new information will be displayed at the bottom line of said scrollable region. On the other hand during a downward scroll, a bottom line of information on the scrollable region of the screen will fade out and new information is added, from the off screen region, of the bit map memory to provide information for a new top line. In addition the system has the ability to reorganize the information in the bit map memory in the event the size or location of the fixed region is to be altered.
摘要翻译：本发明用于具有连接到CRT显示装置的位图存储器的系统，并且CRT显示装置可以显示信息的固定区域和可滚动的信息区域。在优选实施例中，系统使用图形显示控制电路来改变位图存储器中的固定和可滚动区域的起始地址和长度结束值。通过将起始地址改变为每帧一条扫描线，而不会在存储器中实际传输数据，从一个位置到另一个位置，本系统会实现“平滑”滚动。系统能够向上和向下滚动。该系统使用逻辑电路用附加的可滚动信息加载位图存储器的屏幕段，使得作为可滚动信息区域的顶行的（在向上滚动负载中）不再显示，新信息将显示在所述可滚动区域的底线。另一方面，在向下滚动期间，屏幕的可滚动区域的信息的底线将逐渐消失，并且从屏幕外部添加位图映射存储器的新信息以提供新的顶行信息。此外，如果要修改固定区域的大小或位置，系统可以重新组织位图存储器中的信息。

90. 发明授权

US4491834A Display controlling apparatus 失效
标题翻译：显示控制装置
公开(公告)号：US4491834A
公开(公告)日：1985-01-01
申请号：US598360
申请日：1984-04-12
申请人： Tetsuji Oguchi
发明人： Tetsuji Oguchi
IPC分类号： G09G5/34 , G09G1/16
CPC分类号： G09G5/346
摘要： A display control system has a memory for storing display information and a memory access circuit for reading display information out of this memory. This memory access circuit includes a first circuit in which a memory address is set, a second circuit for sequentially varying the memory address by a predetermined value, and a third circuit for adding to the memory address a preset value, which is different from the predetermined value. A control circuit gives a designation of the addresses to the memory, as a result of the cooperation of the second circuit and the third circuit. The control circuit can be achieved so that display information is read while a memory address may be varied by at least two different means (the second and third circuits above). Thus, it becomes possible to selectively designate a part of a memory region and to display the information of the selected memory region.
摘要翻译：显示控制系统具有用于存储显示信息的存储器和用于从该存储器读出显示信息的存储器访问电路。该存储器访问电路包括其中设置存储器地址的第一电路，用于将存储器地址顺序地改变预定值的第二电路，以及用于将存储器地址与预定值不同的预设值相加的第三电路值。作为第二电路和第三电路的协作的结果，控制电路给予存储器地址的指定。可以实现控制电路，使得在存储器地址可以通过至少两个不同装置（上述第二和第三电路）改变时，读取显示信息。因此，可以选择性地指定存储区域的一部分并显示所选存储区域的信息。

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