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81. 发明申请

US20090034415A1 WIRELESS COMMUNICATIONS DEVICE 审中-公开
标题翻译：无线通信设备
公开(公告)号：US20090034415A1
公开(公告)日：2009-02-05
申请号：US11830118
申请日：2007-07-30
申请人： JOHN R. BARR , MARK R. BRAUN , EDGAR H. CALLAWAY, JR. , SCOTT B. DAVIS
发明人： JOHN R. BARR , MARK R. BRAUN , EDGAR H. CALLAWAY, JR. , SCOTT B. DAVIS
IPC分类号： H04L12/26
CPC分类号： G06F13/4059
摘要： A wireless communication device (100) including a high-speed data buffer coupled to a first transceiver by a bus, and an application processor having a data buffer associated with the application processor. The associated data buffer is coupled to a high-speed data buffer and to a second transceiver by the bus, wherein the application processor is configured to control the transfer of data between the associated data buffer and the high-speed data buffer and to control the transfer of data between the associated data buffer and the second transceiver.
摘要翻译：一种包括通过总线耦合到第一收发器的高速数据缓冲器的无线通信设备（100），以及具有与所述应用处理器相关联的数据缓冲器的应用处理器。相关联的数据缓冲器通过总线耦合到高速数据缓冲器和第二收发器，其中应用处理器被配置为控制相关联的数据缓冲器和高速数据缓冲器之间的数据传输，并且控制在相关联的数据缓冲器和第二收发器之间传送数据。

82. 发明授权

US07480837B2 Method of monitoring timeout conditions and device therefor 有权
标题翻译：监控超时条件的方法及其设备
公开(公告)号：US07480837B2
公开(公告)日：2009-01-20
申请号：US11142639
申请日：2005-06-01
申请人： Harold M. Martin , Thang Q. Nguyen , Gus P. Ikonomopoulos
发明人： Harold M. Martin , Thang Q. Nguyen , Gus P. Ikonomopoulos
IPC分类号： G06F11/30
CPC分类号： G06F13/4059
摘要： A maximum timeout time for a communication between devices is determined. A time period is determined for a plurality of time zones based upon the maximum timeout time. A current time zone is updated every time period. A timeout zone for an outstanding transaction is associated with a first time zone to indicate when the outstanding transaction will timeout if not completed. In one embodiment, the time period for each time zone is approximately equal to the maximum timeout period divided by a predetermined number of time zones, which may be the total number of time zones, e.g. eight or sixteen.
摘要翻译：确定设备之间的通信的最大超时时间。基于最大超时时间确定多个时区的时间段。每个时间段都会更新当前时区。未完成交易的超时区域与第一时区相关联，以指示未完成的交易如果未完成则超时。在一个实施例中，每个时区的时间段大约等于最大超时时间除以预定数量的时区，其可以是时区的总数，例如，八十六岁。

83. 发明申请

US20080307444A1 STORAGE ROUTER AND METHOD FOR PROVIDING VIRTUAL LOCAL STORAGE 有权
标题翻译：存储路由器和提供虚拟本地存储的方法
公开(公告)号：US20080307444A1
公开(公告)日：2008-12-11
申请号：US11947499
申请日：2007-11-29
申请人： Geoffrey B. Hoese , Jeffry T. Russell
发明人： Geoffrey B. Hoese , Jeffry T. Russell
IPC分类号： G06F13/00
CPC分类号： G06F13/1668 , G06F3/0601 , G06F3/0605 , G06F3/0607 , G06F3/0661 , G06F3/0664 , G06F3/067 , G06F13/385 , G06F13/4022 , G06F13/4059 , G06F2003/0692 , H04L29/12858 , H04L29/12886 , H04L61/106 , H04L61/6031 , H04L61/6045 , H04L67/1097 , H04L67/2842
摘要： A storage router (56) and storage network (50) provide virtual local storage on remote SCSI storage devices (60, 62, 64) to Fibre Channel devices. A plurality of Fibre Channel devices, such as workstations (58), are connected to a Fibre Channel transport medium (52), and a plurality of SCSI storage devices (60, 62, 64) are connected to a SCSI bus transport medium (54) The storage router (56) interfaces between the Fibre Channel transport medium (52) and the SCSI bus transport medium (54). The storage router (56) maps between the workstations (58) and the SCSI storage devices (60, 62, 64) and implements access controls for storage space on the SCSI storage devices (60, 62, 64). The storage router (56) then allows access from the workstations (58) to the SCSI storage devices (60, 62, 64) using native low level, block protocol in accordance with the mapping and the access controls.
摘要翻译：存储路由器（56）和存储网络（50）向远程SCSI存储设备（60,62,64）向光纤通道设备提供虚拟本地存储。诸如工作站（58）的多个光纤通道设备连接到光纤通道传输介质（52），并且多个SCSI存储设备（60,62,64）连接到SCSI总线传输介质（54））存储路由器（56）在光纤通道传输介质（52）和SCSI总线传输介质（54）之间接口。存储路由器（56）在工作站（58）和SCSI存储设备（60,62,64）之间映射并且实现对SCSI存储设备（60,62,64）上的存储空间的访问控制。存储路由器（56）然后允许根据映射和访问控制使用本地低级别块协议从工作站（58）到SCSI存储设备（60,62,64）的访问。

84. 发明申请

US20080298512A1 DATA PROCESSING APPARATUS 有权
标题翻译：数据处理设备
公开(公告)号：US20080298512A1
公开(公告)日：2008-12-04
申请号：US12106085
申请日：2008-04-18
申请人： Yoshihiro Murakami
发明人： Yoshihiro Murakami
IPC分类号： H04L27/06 , H03D1/00
CPC分类号： G06F13/4059 , H04J3/047 , H04J3/1605 , H04S1/007
摘要： A data processing apparatus includes a channel demultiplexing circuit, a bus, a memory controller and a memory. The channel demultiplexing circuit has a first delay circuit which delays first channel data only of multi-channel data by one cycle and outputs first delayed channel data, a second delay circuit which delays second channel data only of the multi-channel data by one cycle and outputs second delayed channel data, and a channel data holding circuit which stores first coupled data obtained by coupling the first channel data and the first delayed channel data for multiple cycles and stores second coupled data obtained by coupling the second channel data and an output of the second delay circuit for multiple cycles. The channel demultiplexing circuit selectively outputs a first channel data group and a second channel data group to the bus.
摘要翻译：数据处理装置包括信道解复用电路，总线，存储器控制器和存储器。信道解复用电路具有第一延迟电路，该第一延迟电路仅将多通道数据的第一通道数据延迟一个周期，并输出第一延迟通道数据，第二延迟电路仅将多通道数据的第二通道数据延迟一个周期，输出第二延迟信道数据，以及信道数据保持电路，其存储通过将第一信道数据和第一延迟信道数据耦合多个周期获得的第一耦合数据，并存储通过耦合第二信道数据获得的第二耦合数据和第二延迟电路多个周期。信道解复用电路选择性地向总线输出第一信道数据组和第二信道数据组。

85. 发明申请

US20080281996A1 Latency Insensitive FIFO Signaling Protocol 有权
标题翻译：延迟不敏感的FIFO信令协议
公开(公告)号：US20080281996A1
公开(公告)日：2008-11-13
申请号：US12179970
申请日：2008-07-25
申请人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
发明人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
IPC分类号： G06F13/38 , G06F3/00
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。源端计数器跟踪FIFO中可用的空间。在公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。响应于来自接收器域的信令从FIFO读取数据，计数器递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

86. 发明授权

US07451338B2 Clock domain crossing 有权
标题翻译：时钟域交叉
公开(公告)号：US07451338B2
公开(公告)日：2008-11-11
申请号：US11241581
申请日：2005-09-30
申请人： Gregory D. Lemos
发明人： Gregory D. Lemos
IPC分类号： G06F1/01
CPC分类号： G06F13/4059
摘要： Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be transferred are shifted in the first clock domain. The shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain. A stream of sampled bits may be output in the second clock domain. Additional embodiments are described and claimed.
摘要翻译：提供了一种用于实现从一个时钟域到另一个时钟域的数据传输的方法，系统和设备。根据本文提供的描述的一个方面，要传送的数据位在第一时钟域中移位。要传送的数据的移位位可以在第一时钟域的每个时钟信号内的固定时间在第二时钟域采样。可以在第二时钟域中输出采样比特流。描述和要求保护附加的实施例。

87. 发明申请

US20080250170A1 CLOCK MODE DETECTION IN AN ADAPTIVE TWO-WIRE BUS 审中-公开
标题翻译：自适应双线总线中的时钟模式检测
公开(公告)号：US20080250170A1
公开(公告)日：2008-10-09
申请号：US11695762
申请日：2007-04-03
申请人： Stephen J. Sheafor
发明人： Stephen J. Sheafor
IPC分类号： G06F3/00
CPC分类号： G06F13/4059
摘要： Techniques for improving the quality or fidelity of a digital signal transmitted via a two-wire bus interconnect utilizing an open-terminal configuration at one or both end devices of the bus interconnect are disclosed. An intermediate two-wire bus is used to connect two open-terminal-based two-wire busses. A bus adapter device is utilized at each end of the intermediate two-wire bus, whereby the bus adapter device communicates signaling on the corresponding open-terminal-based two-wire bus using open-terminal ports and communicates signaling on the intermediate two-wire bus using push-pull ports. The bus adapter device can utilize control logic to implement a state machine or other function to control the interactions between the different two-wire buses. The bus adapter devices may be implemented as interchangeable integrated circuit devices that can change configuration based on connection, thereby permitting their implementation at either end of a bus transmission system.
摘要翻译：公开了一种用于通过利用总线互连的一端或两端设备处的开放式终端配置通过两线总线互连传输的数字信号的质量或保真度的技术。中间的两线总线用于连接两个基于开放终端的双线总线。在中间双线总线的每端使用总线适配器装置，由此总线适配器装置使用开放式终端端口在相应的基于开放终端的双线总线上进行信令传送，并在中间双线总线总线使用推挽端口。总线适配器装置可以利用控制逻辑来实现状态机或其他功能来控制不同的双线总线之间的相互作用。总线适配器装置可以实现为可互换集成电路装置，其可以基于连接改变配置，从而允许它们在总线传输系统的任一端实现。

88. 发明授权

US07424565B2 Method and apparatus for providing efficient output buffering and bus speed matching 有权
标题翻译：提供有效的输出缓冲和总线速度匹配的方法和装置
公开(公告)号：US07424565B2
公开(公告)日：2008-09-09
申请号：US11280148
申请日：2005-11-16
申请人： Magne Vigulf Sandven , Morten Schanke , Brian Edward Manula
发明人： Magne Vigulf Sandven , Morten Schanke , Brian Edward Manula
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： An interconnect apparatus includes a transaction packet buffer and control logic. The control logic can be operable sequentially to write transaction packets for transmission to the transaction packet buffer and to transmit the buffered transaction packets in sequence to a destination. The control logic can further be operable on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet.
摘要翻译：互连设备包括事务包缓冲器和控制逻辑。控制逻辑可以顺序地可操作地写入事务分组以便传输到事务分组缓冲器并且将缓冲的事务分组顺序发送到目的地。控制逻辑还可以在接收到表示未被接收的发送的交易分组的目的地的控制分组时重新发送未接收到的交易分组以及在未接收的交易之后从交易分组缓冲器发送的交易分组包。

89. 发明申请

US20080133814A1 DATA TRANSFER APPARATUS WITH CONTROL OF BUSES TO OPTIMIZE DATA TRANSFER 有权
标题翻译：数据传输设备控制业务优化数据传输
公开(公告)号：US20080133814A1
公开(公告)日：2008-06-05
申请号：US12028708
申请日：2008-02-08
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/4031 , G06F13/4059 , G06F13/423 , G06F2213/0024
摘要： A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.
摘要翻译：总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

90. 发明申请

US20080130682A1 System and method for communication over an adaptive service bus 有权
标题翻译：通过自适应业务总线进行通信的系统和方法
公开(公告)号：US20080130682A1
公开(公告)日：2008-06-05
申请号：US11607584
申请日：2006-12-01
申请人： Ty Akadiri
发明人： Ty Akadiri
IPC分类号： H04J3/16
CPC分类号： G06F13/4059
摘要： An adaptive service bus comprising adaptable logical components for transporting communications. A configuration of each logical component of the adaptive service bus is determined by receipt of a control message that establishes the behavior of that component. Thereafter, communications that are received by the adaptive service bus are processed in accordance with “rules” established by the configurations. The configuration of the adaptive service bus may be changed in real time to accommodate changes in communications types and/or changes in the processing rule for a particular communication type.
摘要翻译：一种包括用于传送通信的适应性逻辑组件的自适应业务总线。通过接收建立该组件的行为的控制消息来确定自适应业务总线的每个逻辑组件的配置。此后，根据由配置建立的“规则”处理由自适应业务总线接收的通信。自适应业务总线的配置可以实时改变以适应通信类型的变化和/或用于特定通信类型的处理规则的改变。

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