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81. 发明申请

US20130089104A1 System and Method for High-Performance, Low-Power Data Center Interconnect Fabric 有权
公开(公告)号：US20130089104A1
公开(公告)日：2013-04-11
申请号：US13705386
申请日：2012-12-05
申请人： CALXEDA, INC.
发明人： Mark Bradley Davis , David James Borland
IPC分类号： H04L12/56
CPC分类号： H04L45/74 , G06F1/3234 , G06F3/0605 , G06F3/0631 , G06F3/067 , G06F9/5016 , G06F12/0284 , G06F13/00 , G06F13/24 , G06F13/40 , H04L45/00 , H04L45/60 , H04L45/7457 , H04L47/10 , H04L49/109 , H04L49/15 , H04L49/201 , H04L49/25 , H04L49/253 , H04L49/3009 , H04L49/351 , H04L49/356 , Y02B70/16 , Y02B70/30 , Y02B70/32 , Y02D10/14 , Y02D10/151 , Y02D30/32
摘要： A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

82. 发明申请

US20130042086A1 Dynamic Network Adapter Memory Resizing and Bounding for Virtual Function Translation Entry Storage 有权
公开(公告)号：US20130042086A1
公开(公告)日：2013-02-14
申请号：US13561010
申请日：2012-07-28
申请人： Omar Cardona , Vinit Jain , Jayakrishna Kidambi , Renato J. Recio
发明人： Omar Cardona , Vinit Jain , Jayakrishna Kidambi , Renato J. Recio
IPC分类号： G06F12/02
CPC分类号： G06F12/0284 , Y02D10/13
摘要： An approach is provided which a system selects a first virtual function from a plurality of virtual functions executing on a network adapter that includes a memory area. Next, the system allocates, in the memory area, a memory corresponding to the first virtual function. The system then stores one or more translation entries in the allocated memory partition, which are utilized to send data traversing through the first virtual function. As such, the system sends, utilizing one or more of the translation entries, the data packets from the network adapter to one or more destinations. In turn, the system dynamically resizes the memory partition based upon an amount of the memory partition that is utilized to store the one or more translation entries.

83. 发明申请

US20130022040A1 SYSTEM AND METHOD FOR HIGH-PERFORMANCE, LOW-POWER DATA CENTER INTERCONNECT FABRIC WITH BROADCAST OR MULTICAST ADDRESSING 有权
标题翻译：用于高性能，低功率数据中心互连结构的系统和方法，具有广播或多播寻址
公开(公告)号：US20130022040A1
公开(公告)日：2013-01-24
申请号：US13624731
申请日：2012-09-21
申请人： Mark Davis , David James Borland
发明人： Mark Davis , David James Borland
IPC分类号： H04L12/64
CPC分类号： H04L45/74 , G06F1/3234 , G06F3/0605 , G06F3/0631 , G06F3/067 , G06F9/5016 , G06F12/0284 , G06F13/00 , G06F13/24 , G06F13/40 , H04L45/00 , H04L45/60 , H04L45/7457 , H04L47/10 , H04L49/109 , H04L49/15 , H04L49/201 , H04L49/25 , H04L49/253 , H04L49/3009 , H04L49/351 , H04L49/356 , Y02B70/16 , Y02B70/30 , Y02B70/32 , Y02D10/14 , Y02D10/151 , Y02D30/32
摘要： A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
摘要翻译：提供了一种系统和方法，其支持使用支持多个链路的树状或图形拓扑的路由，每个节点在拓扑中指定每条链路为Up，Down或Lateral链路，或两者。该系统可以使用分段MAC架构，其可以具有为内部MAC和外部MAC重新使用MAC IP地址的方法，并且利用通常将MAC的物理信令馈送到交换机中。

84. 发明申请

US20120327697A1 DISTRIBUTED FLASH MEMORY STORAGE MANAGER SYSTEMS 有权
标题翻译：分布式闪存存储管理系统
公开(公告)号：US20120327697A1
公开(公告)日：2012-12-27
申请号：US13603994
申请日：2012-09-05
申请人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： G11C5/06
CPC分类号： G06F12/0284 , G06F12/0692 , G06F2212/1041 , G06F2212/2022
摘要： A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory.
摘要翻译：闪速存储器存储系统可以包括闪存存储器管理器电路的几个模块，每个模块具有一些相关联的闪存。模块可以经由模块的闪速存储器存储管理器电路互连。通过将数据路由到模块的闪速存储器存储电路，系统可能能够将数据写入和/或从与各种模块相关联的闪存中读取数据。由于各种原因，使用这种读写操作，系统也可以重新定位数据。模块的闪存存储电路跟踪闪存中实际数据的位置。

85. 发明申请

US20120290815A1 DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20120290815A1
公开(公告)日：2012-11-15
申请号：US13443465
申请日：2012-04-10
申请人： Hirokazu Takahashi
发明人： Hirokazu Takahashi
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/3885 , G06F9/345 , G06F12/0284 , G06F12/0842 , G06F12/0875 , G06F12/0886 , G06F2212/1016 , G06F2212/455 , G06T1/60
摘要： A data processing apparatus causes multiple processors to carry out a first data process in parallel, and when storing the data processed in parallel in a storage unit, converts the addresses of the data into addresses in the storage unit based on the data cache size of the multiple processors and stores the data. The data stored in the storage unit is then read out, and a second data process is carried out on the read-out data.
摘要翻译：数据处理装置使多个处理器并行地执行第一数据处理，并且当将并行处理的数据存储在存储单元中时，基于数据高速缓存大小将数据的地址转换为存储单元中的地址多个处理器并存储数据。然后读出存储在存储单元中的数据，并对读出的数据执行第二数据处理。

86. 发明授权

US08312201B2 Managing memory allocations loans 有权
标题翻译：管理记忆分配贷款
公开(公告)号：US08312201B2
公开(公告)日：2012-11-13
申请号：US12135494
申请日：2008-06-09
申请人： Matthew D. Fleming
发明人： Matthew D. Fleming
IPC分类号： G06F12/00
CPC分类号： G06F12/023 , G06F12/0284 , G06F12/08 , G06F2212/152
摘要： A mechanism for operating a virtual memory is provided in an operating system. The mechanism detects the existence of a central memory loan pool, identifies a segment of memory that is loanable, and transmits an indicator that the segment is available for loaning to the memory loan pool. The operating system contributing memory can monitor its actual memory capacity and reclaim the loaned segment if the amount of memory available to the loaning operating system (OS) gets below a predetermined value.
摘要翻译：在操作系统中提供了用于操作虚拟存储器的机制。该机制检测到中央存储器贷款池的存在，识别可借贷的存储器段，并发送段可用于借贷给内存贷款池的指标。提供内存的操作系统可以监控其实际的内存容量，并且如果借用操作系统（OS）可用的内存量低于预定值，则回收借出的段。

87. 发明授权

US08281073B2 Information processing apparatus and method of controlling same 有权
标题翻译：信息处理装置及其控制方法
公开(公告)号：US08281073B2
公开(公告)日：2012-10-02
申请号：US12698750
申请日：2010-02-02
申请人： Kenji Hara
发明人： Kenji Hara
IPC分类号： G06F12/08
CPC分类号： G06F12/0866 , G06F12/0284 , G06F12/109 , G06F2212/284 , G06F2212/311
摘要： Disclosed is an information processing apparatus equipped with first and second CPUs, as well as a method of controlling this apparatus. When the first CPU launches an operating system for managing a virtual memory area that includes a first cache area for a device, the first CPU generates specification data, which indicates the corresponding relationship between the first cache and a second cache for the device and provided in a main memory, and transfers the specification data to the second CPU. In accordance with the specification data, the second CPU transfers data, which has been stored in the device, to a physical memory corresponding to a cache to which the first CPU refers. As a result, the first CPU accesses the first cache area is thereby capable of accessing the device at high speed.
摘要翻译：公开了一种配备有第一和第二CPU的信息处理装置，以及控制该装置的方法。当第一CPU启动用于管理包括用于设备的第一高速缓存区域的虚拟存储器区域的操作系统时，第一CPU产生指定数据，其指示用于该设备的第一高速缓存和第二高速缓存之间的对应关系，主存储器，并将规范数据传送到第二CPU。根据规格数据，第二CPU将已经存储在设备中的数据传送到与第一CPU参考的高速缓存相对应的物理存储器。结果，第一CPU访问第一高速缓存区域由此能够高速地访问设备。

88. 发明授权

US08280974B2 Migrating workloads using networked attached memory 有权
标题翻译：使用网络附加内存迁移工作负载
公开(公告)号：US08280974B2
公开(公告)日：2012-10-02
申请号：US11831790
申请日：2007-07-31
申请人： Daniel Edward Herington
发明人： Daniel Edward Herington
IPC分类号： G06F15/167
CPC分类号： G06F12/08 , G06F9/45533 , G06F9/4856 , G06F9/5077 , G06F12/0284 , H04L67/1097
摘要： A network system comprising a plurality of servers communicatively-coupled on a network, a network-attached memory coupled between a first server and a second server of the server plurality, and a memory management logic that executes on selected servers of the server plurality and migrates a virtual machine from the first server to the second server with memory for the virtual machine residing on the network-attached memory.
摘要翻译：一种网络系统，包括通信地耦合在网络上的多个服务器，耦合在服务器多个的第一服务器和第二服务器之间的网络连接的存储器，以及在服务器多个的所选服务器上执行并移动的存储器管理逻辑从第一服务器到第二服务器的虚拟机，其具有位于网络附加存储器上的虚拟机的存储器。

89. 发明申请

US20120124305A1 METHOD AND SYSTEM FOR INTEGRATING DATABASE MEMORY MANAGEMENT IN VIRTUAL MACHINES 有权
标题翻译：用于在虚拟机中集成数据库存储管理的方法和系统
公开(公告)号：US20120124305A1
公开(公告)日：2012-05-17
申请号：US12946940
申请日：2010-11-16
申请人： Boris WEISSMAN , Aleksandr V. MIRGORODSKIY , Ganesh VENKITACHALAM , Feng TIAN
发明人： Boris WEISSMAN , Aleksandr V. MIRGORODSKIY , Ganesh VENKITACHALAM , Feng TIAN
IPC分类号： G06F12/02 , G06F12/12
CPC分类号： G06F12/0223 , G06F9/45533 , G06F12/0284 , G06F12/08 , G06F2009/45583 , G06F2212/151 , G06F2212/163 , G06F2212/657
摘要： Memory of a database management system (DBMS) that is running in a virtual machine is managed using techniques that integrate DBMS memory management with virtual machine memory management. Because of the integration, the effectiveness of DBMS memory management is preserved even though the physical memory allocated to the virtual machine may change during runtime as a result of varying memory demands of other applications, e.g., instances of other virtual machines, running on the same host computer as the virtual machine.
摘要翻译：使用将DBMS内存管理与虚拟机内存管理集成的技术来管理在虚拟机中运行的数据库管理系统（DBMS）的内存。由于集成，即使分配给虚拟机的物理内存可能在运行时间内由于其他应用程序的不同内存需求（例如，运行在其上的其他虚拟机的实例）的结果而改变，DBMS内存管理的有效性也将保持不变主机作为虚拟机。

90. 发明申请

US20120042131A1 Flexible use of extended cache using a partition cache footprint 失效
标题翻译：灵活使用扩展缓存使用分区缓存占用空间
公开(公告)号：US20120042131A1
公开(公告)日：2012-02-16
申请号：US12856682
申请日：2010-08-15
申请人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
发明人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0284 , G06F2212/502 , G06F2212/604
摘要： An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.
摘要翻译：提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小正在由第二处理核心执行。

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