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81. 发明授权

US5873063A LSP speech synthesis device 失效
标题翻译： LSP语音合成装置
公开(公告)号：US5873063A
公开(公告)日：1999-02-16
申请号：US857866
申请日：1997-05-16
申请人： Xingjun Wu , Yihe Sun
发明人： Xingjun Wu , Yihe Sun
IPC分类号： G10L13/02 , G10L19/06 , G10L3/00
CPC分类号： G10L19/07 , G10L13/02
摘要： A speech synthesis application specific integrated circuit (ASIC) based on an Line Spectrum Pair (LSP) scheme. In the ASIC, the LSP parameter is encoded and two's complement fixed-point serial pipeline arithmetic operations with rounding are performed by an LSP speech synthesis digital filter. The operating rate demanded for the ASIC is low, and the elements of the ASIC are mostly in serial shift structure. So, the area of the LSP speech synthesis ASIC is much less than the conventional chip.
摘要翻译：基于线谱对（LSP）方案的语音合成专用集成电路（ASIC）。在ASIC中，对LSP参数进行编码，并通过LSP语音合成数字滤波器进行具有舍入的二进制补码定点串行流水线算术运算。 ASIC要求的运行速度很低，而ASIC的要素主要是串行转换结构。因此，LSP语音合成ASIC的面积远远小于传统芯片。

82. 发明授权

US5867722A Sticky bit detector for a floating-point processor 失效
标题翻译：用于浮点处理器的粘滞位检测器
公开(公告)号：US5867722A
公开(公告)日：1999-02-02
申请号：US15484
申请日：1998-01-28
申请人： Graham B. Whitted, III , Hsiao Shih Chang
发明人： Graham B. Whitted, III , Hsiao Shih Chang
IPC分类号： G06F7/485 , G06F7/50 , G06F9/302 , G06F13/00
CPC分类号： G06F7/485 , G06F9/30014 , G06F7/49952
摘要： A floating-point processor and method detect a sticky bit during a floating point operation. The floating-point processor includes a sticky bit predictor circuit, a bit scanner, an exponent arithmetic circuit, and a mantissa arithmetic logic circuit. Input and output circuitry allow the floating-point processor to communicate with another processor. The bit scanner generates sticky significance values corresponding to the operands. When adding two operands, the sticky bit predictor circuit compares the sticky significance value of the smaller operand with an alignment value in order determine whether to set the sticky bit.
摘要翻译：浮点处理器和方法在浮点运算期间检测粘点。浮点处理器包括粘滞位预测器电路，位扫描器，指数运算电路和尾数运算逻辑电路。输入和输出电路允许浮点处理器与另一个处理器进行通信。位扫描器产生对应于操作数的粘性显着性值。当添加两个操作数时，粘滞位预测器电路将较小操作数的粘性显着值与对准值进行比较，以确定是否设置粘滞位。

83. 发明授权

US5866454A Method of fabricating a capacitor structure for a dynamic random access memory cell with cellular voids 失效
标题翻译：制造具有细胞空隙的动态随机存取存储器单元的电容器结构的方法
公开(公告)号：US5866454A
公开(公告)日：1999-02-02
申请号：US805170
申请日：1997-02-24
申请人： Fang-Ching Chao
发明人： Fang-Ching Chao
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A structure and a method to increase the capacitance of a DRAM capacitor by forming a capacitor electrode with cellular voids to add surface area. According to the method: a transfer transistor with a gate electrode and source-drain electrode regions is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate and the transfer transistor, and the insulating layer is etched to form a contact void for exposing the surface of one of the source-drain electrode areas as a contact. A first conductive layer is formed on the insulating layer and is coupled to the contact through the contact void. On the first conductive layer, at least one middle insulating layer and one middle conductive layer are formed alternately to construct a multiple layer structure. Within the middle insulating layer(s), intercommunicating voids are formed through which the middle conductive layer is coupled to the first conductive layer is coupled to the first conductive layer. Thereafter, the middle conductive layer, the middle insulating layer and the first conductive layer are etched selectively to define an area of a capacitor. The middle insulating layer is removed by isotropic etching to form surface-increasing voids, and a cellular structure as a storage electrode is formed by the first conductive layer and the middle conductive layer. A dielectric layer is formed on the exposed surface of the storage electrode. A second conductive layer as an opposed electrode of the capacitor is then formed on the dielectric layer.
摘要翻译：通过形成具有细胞空隙的电容器电极来增加DRAM电容器的电容的结构和方法以增加表面积。根据该方法：在半导体衬底上形成具有栅极电极和源极 - 漏极电极区域的转移晶体管。在半导体衬底和转移晶体管上形成绝缘层，并且蚀刻绝缘层以形成接触空隙，用于将源极 - 漏极电极区域之一的表面暴露为接触。在绝缘层上形成第一导电层，并通过接触空隙与触点相连。在第一导电层上交替地形成至少一个中间绝缘层和一个中间导电层以构成多层结构。在中间绝缘层中，形成相互连通的空隙，中间导电层耦合到第一导电层与第一导电层耦合。此后，选择性地蚀刻中间导电层，中间绝缘层和第一导电层以限定电容器的面积。通过各向同性蚀刻去除中间绝缘层以形成增加表面的空隙，并且通过第一导电层和中间导电层形成作为存储电极的多孔结构。在存储电极的暴露表面上形成介电层。然后在电介质层上形成作为电容器的相对电极的第二导电层。

84. 发明授权

US5856948A Sychronous memory burn-in method 失效
标题翻译：同步内存老化方法
公开(公告)号：US5856948A
公开(公告)日：1999-01-05
申请号：US9402
申请日：1998-01-20
申请人： Chun-Chieh Huang , Dong-Chie Liou
发明人： Chun-Chieh Huang , Dong-Chie Liou
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C11/401
摘要： A burn-in method for synchronous memory that utilizes synchronous signals for the burn-in operation. Using synchronous clock pulse signals for burning in the synchronous memory is able to exercise the burst output mode and the pipeline function, and hence the optimum burn-in results can be obtained. Furthermore, synchronous burn-in not only can increase the processing speed up to twice the conventional asynchronous burn-in method, but can simulate of the actual working environment of the synchronous memory as well. Moreover, an asynchronous burn-in method can be selected whenever required without any penalty.
摘要翻译：同步存储器的老化方法，利用同步信号进行老化操作。使用同步时钟脉冲信号在同步存储器中进行烧录，可以执行脉冲串输出模式和管线功能，从而可以获得最佳的老化结果。此外，同步老化不仅可以将处理速度提高到常规异步烧录方法的两倍，而且可以模拟同步存储器的实际工作环境。此外，可以在任何需要时选择异步老化方法，而不会造成任何惩罚。

85. 发明授权

US5851879A Method for fabricating compact contactless trenched flash memory cell 失效
标题翻译：制造紧凑型非接触式沟槽闪存单元的方法
公开(公告)号：US5851879A
公开(公告)日：1998-12-22
申请号：US786907
申请日：1997-01-22
申请人： Ruei-Ling Lin , Ching-Hsiang Hsu , Gary Hong
发明人： Ruei-Ling Lin , Ching-Hsiang Hsu , Gary Hong
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.
摘要翻译：公开了一种用于制造用于半导体EEPROM器件的紧凑型非接触式沟槽闪存阵列的方法。闪存阵列包括多个存储单元单元。每个单元单元包括体线，源极和漏极区域以及在硅晶片衬底上构造的堆叠栅极。源极和漏极区域是掩埋区域，并且主体线被周围的掩埋源极/漏极区域和形成为深切割到晶片的衬底的沟槽隔离。层叠栅极包括第一多晶硅层，氧化物 - 氮化物 - 氧化物构造，第二多晶硅层，焊盘氧化物层和氮化物层。源极和漏极掩埋区域夹着体线，并且堆叠的栅极基本上直接位于身体线上方。闪存阵列没有短通道效应的严重问题。

86. 发明授权

US5851872A Method of fabricating dynamic random access memory 失效
标题翻译：制作动态随机存取存储器的方法
公开(公告)号：US5851872A
公开(公告)日：1998-12-22
申请号：US627128
申请日：1996-04-03
申请人： Hwi-Huang Chen , Gary Hong
发明人： Hwi-Huang Chen , Gary Hong
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method of fabricating a DRAM which includes a capacitor and a metal oxide semiconductor field effect transistor. A field oxide layer is formed on a silicon substrate. A gate oxide layer is formed on the silicon substrate. A first polysilicon layer is deposited on the gate oxide layer. An insulator is deposited on the first polysilicon layer. A first silicon nitride layer is deposited on the insulator. The first silicon nitride layer, the insulator, the first polysilicon layer and the gate oxide layer are processed to form a gate electrode. First spacers are formed between the insulator and the substrate on sidewall on opposite sides of the gate electrode. Source-drain regions are formed on the substrate on the opposite sides of the gate electrode. A contact window is formed on the drain electrode. Second spacers are formed on surfaces of the first spacers which are adjacent to the contact window. A second silicon nitride layer is deposited on a surface of the first silicon nitride layer and a surface of the first spacers which are remote from the contact window. A second polysilicon layer is deposited on the contact window as a charge storage electrode of the capacitor. The first silicon nitride layer and the second silicon nitride layer are removed. A dielectric layer is deposited on the surface of the second polysilicon layer. A third polysilicon layer is deposited on the dielectric layer as the cell plate of the capacitor.
摘要翻译：一种制造DRAM的方法，其包括电容器和金属氧化物半导体场效应晶体管。在硅衬底上形成场氧化物层。在硅衬底上形成栅氧化层。第一多晶硅层沉积在栅极氧化物层上。绝缘体沉积在第一多晶硅层上。第一氮化硅层沉积在绝缘体上。第一氮化硅层，绝缘体，第一多晶硅层和栅极氧化物层被加工以形成栅电极。在栅电极的相对侧上的侧壁上的绝缘体和衬底之间形成第一间隔物。源极 - 漏极区域形成在栅电极的相对侧上的衬底上。在漏电极上形成接触窗。第二间隔件形成在与接触窗相邻的第一间隔件的表面上。第二氮化硅层沉积在第一氮化硅层的表面上和第一间隔物的远离接触窗的表面上。第二多晶硅层作为电容器的电荷存储电极沉积在接触窗上。去除第一氮化硅层和第二氮化硅层。介电层沉积在第二多晶硅层的表面上。第三多晶硅层沉积在电介质层上作为电容器的单元板。

87. 发明授权

US5805085A Apparatus and method for scanning a key matrix 失效
标题翻译：用于扫描键矩阵的装置和方法
公开(公告)号：US5805085A
公开(公告)日：1998-09-08
申请号：US686945
申请日：1996-07-26
申请人： Jerry Hsu , Wesley Jehng
发明人： Jerry Hsu , Wesley Jehng
IPC分类号： H03M11/20 , H03K17/94
CPC分类号： H03M11/20
摘要： An apparatus and method for scanning a triangular or trapezoidal key matrix for data input by depressing keys of a keypad. The key matrix allows an increased number of keyswitches to be provided on the key matrix while reducing the number of I/O ports on the I/O interface. The apparatus includes an I/O interface connecting the keypad to the CPU. The keypad I/O interface is provided with m I/O ports, where m is plural integer. Through detecting the voltage levels of these I/O ports, the CPU is able to determine which key on the keypad is being depressed. A triangular key matrix is constructed with a set of m code lines and at least one auxiliary code line arranged in such a way as to form a triangular array of m.times.(m+1)/2 cross-points. Each cross-point is provided with a keyswitch associated with a key on the keypad. The m code lines are connected correspondingly to the m I/O ports on the keypad I/O interface. In another embodiment, a trapezoidal key matrix is constructed with m code lines and two auxiliary code line including a ground line and a power line arranged in such a way as to form an m-by-(m+1) trapezoidal array of m.times.(m+3)/2 cross-points. The method according to the invention is performed by the apparatus to determine which key is being depressed and carry out various actions according to the function of the key being depressed.
摘要翻译：一种用于通过按下键盘的键来扫描用于数据输入的三角形或梯形键矩阵的装置和方法。密钥矩阵允许在密钥矩阵上提供增加的密钥交换数量，同时减少I / O接口上的I / O端口数量。该装置包括将键盘连接到CPU的I / O接口。键盘I / O接口配有m个I / O端口，其中m为多个整数。通过检测这些I / O端口的电压电平，CPU能够确定键盘上的哪个键被按下。三角形键矩阵由一组m个码线和至少一个辅助码线构成，以形成mx（m + 1）/ 2个交叉点的三角阵列。每个交叉点设置有与键盘上的键相关联的钥匙开关。 m代码行相应地连接到键盘I / O接口上的m个I / O端口。在另一个实施例中，梯形键矩阵由m个码线和两个辅助码线构成，包括接地线和电力线，以形成m×（m + 1）个梯形阵列mx（ m + 3）/ 2个交叉点。根据本发明的方法由设备执行以确定哪个键被按下，并且根据按下的键的功能执行各种动作。

88. 发明授权

US5796142A SOI compact contactless flash memory cell 失效
标题翻译： SOI紧凑型非接触式闪存单元
公开(公告)号：US5796142A
公开(公告)日：1998-08-18
申请号：US786908
申请日：1997-01-22
申请人： Ruei-Ling Lin , Ching-Hsiang Hsu , Gary Hong
发明人： Ruei-Ling Lin , Ching-Hsiang Hsu , Gary Hong
IPC分类号： H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/788
CPC分类号： H01L29/7883 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203
摘要： A compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed. Metal lines leading into the contact openings are then formed for interconnecting the memory cells in the flash memory array with peripheral control circuits of the semiconductor EEPROM devices.
摘要翻译：一种用于具有多个存储单元单元的半导体EEPROM器件的紧凑型非接触式闪存阵列。闪存阵列的场氧化物层首先在SOI晶片的表面上生长。然后生长栅极氧化物层。然后通过图案化第一多晶硅层形成浮栅。形成闪存阵列的源/漏掩埋位线。沉积第一个BPSG（硼磷硅酸盐玻璃）层，然后退回并回蚀刻。形成氧化物 - 氮化物 - 氧化物层。第二多晶硅层沉积有原位涂料。然后形成一个WSix层。用于闪存阵列的堆叠栅极通过图案化形成为形成的氧化物 - 氮化物 - 氧化物，第二多晶硅和WSix层。堆叠的栅极然后用第二个BPSG层覆盖。形成用于源极/漏极掩埋线的接触开口。然后形成导入接触开口的金属线，以将闪存阵列中的存储单元与半导体EEPROM器件的外围控制电路互连。

89. 发明授权

US5793659A Method of modular reduction and modular reduction circuit 失效
标题翻译：模块化减少和模块化还原电路的方法
公开(公告)号：US5793659A
公开(公告)日：1998-08-11
申请号：US730197
申请日：1996-10-15
申请人： Hong-Yi Chen , Wei-Xin Gai
发明人： Hong-Yi Chen , Wei-Xin Gai
IPC分类号： G06F7/72 , H04K1/00
CPC分类号： G06F7/72
摘要： A method of modular reduction P mod Q based on a precomputation. Two quantities are precomputed and stored in a look-up table. Based on these stored precomputed quantities, two stages of partial modular reduction are performed. The result of the second stage of partial modular reduction is then adjusted according to the value of Q, to determine the modular reduction result. The modular reduction result may be provided to variable radix multiplication logic circuitry.
摘要翻译：基于预先计算的模块化减少P mod Q的方法。预先计算两个数量并存储在查找表中。基于这些存储的预计算量，执行两个阶段的部分模块化减少。然后根据Q的值调整部分模块化的第二阶段的结果，以确定模块化的减少结果。可以将模块化减少结果提供给可变基乘法逻辑电路。

90. 发明授权

US5789290A Polysilicon CMP process for high-density DRAM cell structures 失效
标题翻译：用于高密度DRAM单元结构的多晶硅CMP工艺
公开(公告)号：US5789290A
公开(公告)日：1998-08-04
申请号：US806698
申请日：1997-02-26
申请人： Shih-Wei Sun
发明人： Shih-Wei Sun
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： Pass transistors are formed on the active device regions of a substrate and a layer of silicon oxide is deposited over the transistors and the surface of the layer of silicon oxide is planarized. A thin layer of silicon nitride is deposited on the oxide layer and then vias are opened through the silicon nitride and silicon oxide layers to expose one of the source/drain regions of each of the pass transistors in the memory array. A layer of polysilicon is deposited so as to extend through the vias, forming polysilicon vertical interconnects in contact with the source/drain regions of the pass transistors and then the layer of polysilicon is patterned to form capacitor bottom plates, with each of the capacitor bottom plates connected to a corresponding source/drain region. A second layer of silicon oxide is deposited to cover the capacitor bottom plates and photolithography is performed to provide a plurality of openings through the second silicon oxide layer to each of the capacitor bottom plates. Polysilicon is deposited to fill each of the openings and chemical mechanical polishing is performed to remove excess polysilicon using the silicon oxide layer as a polish stop. The second oxide layer is stripped to leave the capacitor bottom plates with fins or posts extending vertically from the bottom plates. A capacitor dielectric is then formed over the capacitor bottom electrodes, capacitor upper electrodes are formed, and further processing continues in the conventional manner.
摘要翻译：通过晶体管形成在衬底的有源器件区域上，并且氧化硅层沉积在晶体管上，并且氧化硅层的表面被平坦化。在氧化物层上沉积一薄层氮化硅，然后通过氮化硅和氧化硅层开放通孔，以暴露存储器阵列中每个传输晶体管的源/漏区之一。沉积多晶硅层以延伸穿过通孔，形成与传导晶体管的源极/漏极区域接触的多晶硅垂直互连，然后将多晶硅层图案化以形成电容器底板，其中每个电容器底部连接到相应的源/漏区的板。沉积第二层氧化硅以覆盖电容器底板，并进行光刻以提供穿过第二氧化硅层的多个开口到每个电容器底板。沉积多晶硅以填充每个开口，并进行化学机械抛光以使用氧化硅层作为抛光停止来除去多余的多余硅。剥离第二氧化物层以离开电容器底板，其中鳍片或柱从底板垂直延伸。然后在电容器底部电极上形成电容器电介质，形成电容器上部电极，并且以常规方式继续进行进一步的处理。

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