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    • 81. 发明申请
    • MULTILINGUAL SOFTWARE TESTING TOOL
    • 多功能软件测试工具
    • US20080263526A1
    • 2008-10-23
    • US11736716
    • 2007-04-18
    • Rodrigo Andres UrraXin GuoWilliam Soon Hock Tay
    • Rodrigo Andres UrraXin GuoWilliam Soon Hock Tay
    • G06F9/45G06F17/00
    • G06F11/3684
    • A software product testing system may include a knowledge base with a data set that includes multiple possible actions and, for each action, language-specific format rules for inputs and outputs associated with the action. The software product testing system may include a test case generator that selects a test case in a target language for a software product. The test case may include a selected action to be taken by a software product, an input to prompt the action, and an expected output that corresponds to the selected action and the input. The expected output has a format corresponding to a language-specific format rule of the target language. The software product testing system may also include a test verifier that determines whether an output generated by application of the test case to the software product matches the expected output.
    • 软件产品测试系统可以包括具有包括多个可能动作的数据集的知识库,并且对于每个动作,可以包括与该动作相关联的输入和输出的针对语言的格式规则。 软件产品测试系统可以包括测试用例发生器,其以软件产品的目标语言选择测试用例。 测试用例可以包括由软件产品选择的动作,用于提示动作的输入以及对应于所选动作和输入的预期输出。 期望的输出具有与目标语言的语言特定格式规则相对应的格式。 软件产品测试系统还可以包括测试验证器,其确定通过将测试用例应用到软件产品产生的输出是否与预期输出匹配。
    • 85. 发明授权
    • Method for producing a low defect homogeneous oxynitride
    • 低缺陷均匀氮氧化物的制造方法
    • US06991987B1
    • 2006-01-31
    • US10306382
    • 2002-11-27
    • Xin GuoNian YangZhigang Wang
    • Xin GuoNian YangZhigang Wang
    • H01L21/8247
    • H01L21/28273C23C16/0218C23C16/0227C23C16/308H01L21/3144
    • A process technology effectuates production of low defect homogeneous oxynitride, which can be applied in tunneling dielectrics with high dielectric constants and low barrier heights for flash memory devices, and as gate oxide for ultra-thin logic devices. The process technology involves varying the oxygen content in a the homogeneous oxynitride film comprising a part of the flash memory device, which effectively increases the dielectric constant of the oxynitride film and lowers its barrier height. In one such process, a controlled co-flow of N2O is introduced into a CVD deposition process. This process effectuates production of a oxynitride film with uniform distributions of nitrogen and oxygen throughout.
    • 一种工艺技术可以实现低缺陷均匀氮氧化物的生产,其可以应用于具有高介电常数的隧道电介质和用于闪存器件的低屏障高度,以及用作超薄逻辑器件的栅极氧化物。 该工艺技术涉及改变包括闪存器件的一部分的均匀氮氧化物膜中的氧含量,其有效地增加氧氮化物膜的介电常数并降低其势垒高度。 在一种这样的方法中,将N 2 O 2的受控共流引入到CVD沉积工艺中。 该方法实现了氮气和氧气的均匀分布的氮氧化物膜的生产。
    • 86. 发明授权
    • Compensated oscillator circuit for charge pumps
    • 电荷泵补偿振荡电路
    • US06888763B1
    • 2005-05-03
    • US10358498
    • 2003-02-04
    • Xin Guo
    • Xin Guo
    • G11C5/14G11C7/00
    • G11C5/145
    • A charge pump oscillator circuit with compensation for variations in process and operating environment. The charge pump oscillator is designed with a rolloff characteristic that enables operation at both weak and strong process corners without excessive power consumption. Composite resistors in the oscillator circuit are composed of component resistors that are fabricated with different processes, e.g., implant and deposition. The resistance of the composite resistor is thus in order to provide compensation for variations in processing and operating environment. The composite resistor may be used as a feedback loop resistor, or may be used as a source degenerate resistor to control the supply current to the oscillator.
    • 电荷泵振荡器电路,具有对工艺和操作环境变化的补偿。 电荷泵振荡器设计具有滚降特性,可在弱过程角和强加工拐角处进行操作,而无需过多的功耗。 振荡器电路中的复合电阻器由通过不同工艺(例如,植入和沉积)制造的元件电阻组成。 因此,复合电阻器的电阻是为了对处理和操作环境的变化提供补偿。 复合电阻器可以用作反馈回路电阻器,或者可以用作源极简并电阻器来控制到振荡器的电源电流。
    • 87. 发明授权
    • Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices
    • 用于减少薄栅极氧化物上的浅沟槽隔离边缘薄化的方法,以提高高性能闪存器件的外围晶体管可靠性和性能
    • US06825083B1
    • 2004-11-30
    • US10126814
    • 2002-04-19
    • Nian YangJohn Jianshi WangXin GuoTien-Chun Yang
    • Nian YangJohn Jianshi WangXin GuoTien-Chun Yang
    • H01L21336
    • H01L27/11526H01L27/105H01L27/11546
    • A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices 480 in an integrated circuit 400 comprising flash memory devices 380, and both thick 390 and thin 480 gate transistor devices. The method begins by forming a tunnel oxide layer 310 over a semiconductor substrate 430 for the formation of the flash memory devices 380 (step 220). A mask 350 is formed over the thin gate transistor devices 480 to inhibit formation of a thick gate oxide layer 360 for the formation of the thick gate transistor devices 390 (step 230). The mask 350 reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer 360 before forming a thin oxide layer 410 for the thin gate transistor devices 480.
    • 一种半导体集成电路制造方法。 具体地,本发明的一个实施例公开了一种用于减少硅的浅沟槽隔离(STI)角凹槽的方法,以便在包括闪存器件380的集成电路400中减少外围薄栅晶体管器件480的STI边缘变薄,以及两者 厚390和薄型480栅极晶体管器件。 该方法开始于在半导体衬底430上形成隧道氧化物层310以形成闪存器件380(步骤220)。 掩模350形成在薄栅极晶体管器件480上,以阻止形成厚栅极氧化物层360以形成厚栅极晶体管器件390(步骤230)。 掩模350通过在形成用于薄栅极晶体管器件480的薄氧化物层410之前消除厚栅极氧化层360的去除来减少浅沟槽隔离(STI)凹陷。
    • 88. 发明授权
    • Memory circuit for providing word line redundancy in a memory sector
    • 用于在存储器扇区中提供字线冗余的存储器电路
    • US06778437B1
    • 2004-08-17
    • US10635974
    • 2003-08-07
    • Michael AchterXin Guo
    • Michael AchterXin Guo
    • G11C1604
    • G11C29/82G11C16/08G11C16/3477
    • According to one embodiment, the memory circuit comprises a memory sector having a plurality of memory cells. Each of the plurality of memory cells has a gate connected to a corresponding word line, where each corresponding word line is further connected to an output of a corresponding decoding circuit. Each corresponding decoding circuit receives a corresponding vertical word line signal, a corresponding global word line signal, and a corresponding sector supply voltage. The corresponding sector supply voltage is capable of supplying an erase voltage, such as −9 V for a negative gate erase memory device, for example. With this arrangement, the corresponding decoding circuit is capable of selectively excluding the corresponding word line from receiving the erase voltage during the erase operation.
    • 根据一个实施例,存储器电路包括具有多个存储单元的存储器扇区。 多个存储单元中的每一个具有连接到相应字线的栅极,其中每个对应的字线进一步连接到对应的解码电路的输出。 每个对应的解码电路接收对应的垂直字线信号,对应的全局字线信号和对应的扇区电源电压。 例如,相应的扇区电源电压能够提供擦除电压,例如用于负栅极擦除存储器件的-9V。 利用这种布置,相应的解码电路能够在擦除操作期间选择性地排除相应的字线接收擦除电压。