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81. 发明申请

US20080121994A1 DEEP JUNCTION SOI MOSFET WITH ENHANCED EDGE BODY CONTACTS 失效
标题翻译：具有增强边缘接触体的DEEP JUNCTION SOI MOSFET
公开(公告)号：US20080121994A1
公开(公告)日：2008-05-29
申请号：US11564352
申请日：2006-11-29
申请人： Thomas W. Dyer , Zhijiong Luo , Jack A. Mandelman
发明人： Thomas W. Dyer , Zhijiong Luo , Jack A. Mandelman
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78615 , H01L29/66772 , H01L29/78603 , H01L29/78618
摘要： A semiconductor structure is provided that has body contacts that are located at the edges of the device channel and a buried insulating region under the device channel that is shallower than the buried insulating regions under the source/drain junctions. A method of forming such a semiconductor structure is also described. The inventive method provides for self-alignment of the various features mentioned above with the gate conductor of the structure.
摘要翻译：提供半导体结构，其具有位于器件沟道的边缘处的体接触以及在器件沟道下方比在源极/漏极结下方的掩埋绝缘区域浅的掩埋绝缘区域。还描述了形成这种半导体结构的方法。本发明的方法提供了上述各种特征与结构的栅极导体的自对准。

82. 发明授权

US07666721B2 SOI substrates and SOI devices, and methods for forming the same 失效
标题翻译： SOI衬底和SOI器件及其形成方法
公开(公告)号：US07666721B2
公开(公告)日：2010-02-23
申请号：US11308292
申请日：2006-03-15
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/0653 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.
摘要翻译：提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。可以在SOI衬底中形成一个或多个场效应晶体管（FET）。例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

83. 发明申请

US20080283962A1 SELF-ALIGNED AND EXTENDED INTER-WELL ISOLATION STRUCTURE 失效
标题翻译：自对准和扩展的隔离隔离结构
公开(公告)号：US20080283962A1
公开(公告)日：2008-11-20
申请号：US11748521
申请日：2007-05-15
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/3086 , H01L21/823878
摘要： A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.
摘要翻译：从衬垫层形成基座，使得底座的两个边缘与植入的孔的边界重合。通过沉积保形介电层在基座上形成延伸基座。扩展基座的面积暴露在下方的半导体表面凹陷到凹陷深度。包括至少一个井内隔离沟槽的其它沟槽被光刻图案化。在反应离子蚀刻之后，形成阱间隔离沟槽和至少一个阱间隔离沟槽。与现有技术的结构相比，由于较深的底面，间隙隔离沟槽的宽度可能会降低。在井间隔离结构下面的p阱和n阱之间的边界与井间隔离结构的中间自对准。

84. 发明授权

US07485516B2 Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation 失效
标题翻译：在氧化之前将氮离子注入到半导体衬底中用于偏移间隔物形成的方法
公开(公告)号：US07485516B2
公开(公告)日：2009-02-03
申请号：US11164376
申请日：2005-11-21
申请人： Thomas W. Dyer , Jinhong Li , Zhijiong Luo
发明人： Thomas W. Dyer , Jinhong Li , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28247
摘要： A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.
摘要翻译：形成集成电路器件的方法包括在半导体的一部分上形成栅电极堆叠。堆叠包括其上方具有栅电极的栅介质层。将双原子氮和/或氮原子从堆叠中以最低能量小于或等于10keV的双原子氮并且在小于或等于5keV的最大能量下，在低于或等于等于1000℃，时间小于或等于30分钟。然后在堆叠的侧壁上形成氧化硅偏移间隔物。在偏移间隔物之外的衬底中形成源极/漏极延伸区域。在氮注入层的另一部分上的偏移间隔物的外表面上形成氮化物侧壁间隔物。然后在侧壁间隔物之外形成衬底中的源极/漏极区域。

85. 发明授权

US10096717B2 MOSFET and method for manufacturing the same 有权
公开(公告)号：US10096717B2
公开(公告)日：2018-10-09
申请号：US13510407
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265 , H01L29/66 , H01L21/74
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.

86. 发明授权

US09583622B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09583622B2
公开(公告)日：2017-02-28
申请号：US14407263
申请日：2012-07-06
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
IPC分类号： H01L27/12 , H01L29/78 , H01L29/66 , H01L29/732 , H01L29/737 , H01L29/786 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/324 , H01L21/762 , H01L29/04 , H01L29/06 , H01L29/16 , H01L29/161
CPC分类号： H01L29/7849 , H01L21/0245 , H01L21/02513 , H01L21/265 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/76254 , H01L21/76283 , H01L29/04 , H01L29/0653 , H01L29/16 , H01L29/161 , H01L29/66242 , H01L29/66272 , H01L29/66568 , H01L29/66772 , H01L29/732 , H01L29/7371 , H01L29/78654
摘要： The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device.
摘要翻译：本发明公开了一种半导体结构及其制造方法，其特征在于，在基板上设置基板，形成应力层，埋入氧化物层，SOI层，在应力层中形成布置在特定位置的应力层的掺杂区域; 在所述SOI层上形成氧化物层和氮化物层，形成蚀刻所述氮化物层，所述氧化物层，所述SOI层和所述埋入氧化物层的第一沟槽，并停止在所述应力层的上表面上，以及暴露应力层的掺杂区域的至少一部分; 通过所述第一沟槽的湿蚀刻形成空腔以移除所述应力层的掺杂区域; 通过用多晶硅填充空腔并回蚀而形成应力层的多晶硅区域和第二沟槽; 通过填充第二沟槽形成隔离区域。在本发明中公开的半导体结构及其制造方法通过根据器件类型在特定位置引入应力层和应力诱导区域来为半导体器件的沟道提供有利的应力，以有助于提高半导体器件。

87. 发明授权

US09548317B2 FDSOI semiconductor structure and method for manufacturing the same 有权
标题翻译： FDSOI半导体结构及其制造方法
公开(公告)号：US09548317B2
公开(公告)日：2017-01-17
申请号：US14397586
申请日：2012-05-22
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/84 , H01L27/12 , H01L29/66 , H01L29/786 , H01L21/02 , H01L21/266 , H01L21/306 , H01L21/308 , H01L21/768 , H01L29/78 , H01L21/74 , H01L21/265 , H01L29/165
CPC分类号： H01L27/1203 , H01L21/02529 , H01L21/02532 , H01L21/2652 , H01L21/266 , H01L21/30604 , H01L21/3081 , H01L21/743 , H01L21/76897 , H01L21/84 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/78 , H01L29/78612 , H01L29/78648
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which then connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which then saves device area and simplifies manufacturing process accordingly.
摘要翻译：本发明提供了一种制造半导体结构的方法，其包括以下步骤：提供基底，其基本层向上依次包括掩埋隔离层，埋地层，超薄绝缘掩埋层和表面活性层对埋地层进行离子注入掺杂; 在衬底上形成栅极堆叠，侧壁间隔物和源极/漏极区域; 在覆盖栅极堆叠和源极/漏极区域的衬底上形成掩模层，并蚀刻掩模层以暴露源极区域; 蚀刻源极区域下的源极区域和超薄绝缘掩埋层，形成暴露埋入地层的开口; 通过外延工艺填充开口以形成埋地层的接触塞。因此，本发明还提供一种半导体结构。本发明提出了一种掩埋地层接触塞的形成，其然后将掩埋地层电连接到源极区，从而提高半导体器件在阈值电压上的控制能力，抑制短沟道效应并提高器件性能; 而不需要独立的接触来构建埋地层，从而节省设备面积并相应地简化制造过程。

88. 发明授权

US09087691B2 Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same 有权
标题翻译：石墨烯纳米带的制造方法，其制造方法及其制造方法
公开(公告)号：US09087691B2
公开(公告)日：2015-07-21
申请号：US13510390
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/20 , H01L21/36 , H01L21/02 , H01L29/775 , H01L29/06 , H01L29/16 , H01L29/20 , H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , B82Y30/00
CPC分类号： H01L21/0242 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02422 , H01L21/02488 , H01L21/02491 , H01L21/02507 , H01L21/02527 , H01L21/02639 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/66742 , H01L29/775 , H01L29/78684 , H01L29/78696
摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
摘要翻译：提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。在所述至少一个石墨烯纳米带的每个中设置有沟道区。在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。沟道区位于源区和漏区之间。栅电介质位于至少一个石墨烯纳米带上。栅极电介质上的栅极导体。源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

89. 发明授权

US09018739B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09018739B2
公开(公告)日：2015-04-28
申请号：US13060468
申请日：2010-09-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/04 , H01L29/78 , H01L29/10 , H01L29/165 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7834 , H01L29/045 , H01L29/105 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.
摘要翻译：本申请公开了一种半导体器件及其制造方法。半导体器件包括半导体衬底; 半导体衬底上的第一半导体层; 围绕所述第一半导体层的第二半导体层; 形成在第一半导体层上的高k电介质层和栅极导体; 形成在第二半导体层中的源/漏区，其中第二半导体层具有与第一半导体层接触的倾斜侧壁。半导体器件具有增加的输出电流，增加的操作速度以及由于高移动性的沟道区域而导致的功率消耗降低。

90. 发明授权

US09012274B2 Method of manufacturing a semiconductor fin using sacrificial layer 有权
标题翻译：使用牺牲层制造半导体翅片的方法
公开(公告)号：US09012274B2
公开(公告)日：2015-04-21
申请号：US13580965
申请日：2012-05-14
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/84 , H01L21/20 , H01L27/12 , H01L29/06 , H01L29/66
CPC分类号： H01L21/20 , H01L27/1211 , H01L29/0657 , H01L29/66795
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming an insulating film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, an oxide film is formed on the sidewalls of the two semiconductor fins that are far away from each other, while only the sidewalls of the two semiconductor fins that are opposite to each other are exposed, such that conventional operations may be easily performed to the sidewalls opposite to each other in the subsequent process.
摘要翻译：本发明提供一种制造半导体结构的方法，包括以下步骤：提供半导体衬底，在半导体衬底上形成绝缘层，并在绝缘层上形成半导体基底层; 在所述半导体基底层上形成包围所述牺牲层的牺牲层和间隔物，并且通过以所述间隔物作为掩模来蚀刻所述半导体基底层以形成半导体本体; 在半导体主体的侧壁上形成绝缘膜; 去除位于牺牲层下方的牺牲层和半导体本体以形成第一半导体鳍片和第二半导体鳍片。相应地，本发明还提供一种半导体结构。在本发明中，在远离彼此的两个半导体翅片的侧壁上形成氧化膜，只有两个相互相对的两个半导体翅片的侧壁露出，这样常规的操作可以是在随后的过程中容易地对彼此相对的侧壁进行。

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