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81. 发明申请

US20080121994A1 DEEP JUNCTION SOI MOSFET WITH ENHANCED EDGE BODY CONTACTS 失效
标题翻译：具有增强边缘接触体的DEEP JUNCTION SOI MOSFET
公开(公告)号：US20080121994A1
公开(公告)日：2008-05-29
申请号：US11564352
申请日：2006-11-29
申请人： Thomas W. Dyer , Zhijiong Luo , Jack A. Mandelman
发明人： Thomas W. Dyer , Zhijiong Luo , Jack A. Mandelman
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78615 , H01L29/66772 , H01L29/78603 , H01L29/78618
摘要： A semiconductor structure is provided that has body contacts that are located at the edges of the device channel and a buried insulating region under the device channel that is shallower than the buried insulating regions under the source/drain junctions. A method of forming such a semiconductor structure is also described. The inventive method provides for self-alignment of the various features mentioned above with the gate conductor of the structure.
摘要翻译：提供半导体结构，其具有位于器件沟道的边缘处的体接触以及在器件沟道下方比在源极/漏极结下方的掩埋绝缘区域浅的掩埋绝缘区域。还描述了形成这种半导体结构的方法。本发明的方法提供了上述各种特征与结构的栅极导体的自对准。

82. 发明授权

US07666721B2 SOI substrates and SOI devices, and methods for forming the same 失效
标题翻译： SOI衬底和SOI器件及其形成方法
公开(公告)号：US07666721B2
公开(公告)日：2010-02-23
申请号：US11308292
申请日：2006-03-15
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/0653 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.
摘要翻译：提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。可以在SOI衬底中形成一个或多个场效应晶体管（FET）。例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

83. 发明申请

US20080283962A1 SELF-ALIGNED AND EXTENDED INTER-WELL ISOLATION STRUCTURE 失效
标题翻译：自对准和扩展的隔离隔离结构
公开(公告)号：US20080283962A1
公开(公告)日：2008-11-20
申请号：US11748521
申请日：2007-05-15
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/3086 , H01L21/823878
摘要： A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.
摘要翻译：从衬垫层形成基座，使得底座的两个边缘与植入的孔的边界重合。通过沉积保形介电层在基座上形成延伸基座。扩展基座的面积暴露在下方的半导体表面凹陷到凹陷深度。包括至少一个井内隔离沟槽的其它沟槽被光刻图案化。在反应离子蚀刻之后，形成阱间隔离沟槽和至少一个阱间隔离沟槽。与现有技术的结构相比，由于较深的底面，间隙隔离沟槽的宽度可能会降低。在井间隔离结构下面的p阱和n阱之间的边界与井间隔离结构的中间自对准。

84. 发明授权

US07485516B2 Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation 失效
标题翻译：在氧化之前将氮离子注入到半导体衬底中用于偏移间隔物形成的方法
公开(公告)号：US07485516B2
公开(公告)日：2009-02-03
申请号：US11164376
申请日：2005-11-21
申请人： Thomas W. Dyer , Jinhong Li , Zhijiong Luo
发明人： Thomas W. Dyer , Jinhong Li , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28247
摘要： A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.
摘要翻译：形成集成电路器件的方法包括在半导体的一部分上形成栅电极堆叠。堆叠包括其上方具有栅电极的栅介质层。将双原子氮和/或氮原子从堆叠中以最低能量小于或等于10keV的双原子氮并且在小于或等于5keV的最大能量下，在低于或等于等于1000℃，时间小于或等于30分钟。然后在堆叠的侧壁上形成氧化硅偏移间隔物。在偏移间隔物之外的衬底中形成源极/漏极延伸区域。在氮注入层的另一部分上的偏移间隔物的外表面上形成氮化物侧壁间隔物。然后在侧壁间隔物之外形成衬底中的源极/漏极区域。

85. 发明授权

US09263581B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09263581B2
公开(公告)日：2016-02-16
申请号：US14394802
申请日：2012-05-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L23/62 , H01L29/78 , H01L29/66 , H01L29/786 , H01L21/265 , H01L21/324 , H01L29/06
CPC分类号： H01L29/7849 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L29/0649 , H01L29/66545 , H01L29/66583 , H01L29/66772 , H01L29/78654
摘要： A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.
摘要翻译：一种制造半导体结构的方法包括以下步骤：在SOI衬底上提供SOI衬底并形成栅极结构; 通过使用栅极结构作为掩模来注入离子以在半导体结构中引起应力，以形成位于栅极结构两侧的SOI衬底上的BOX层下方的应力诱导区域。还公开了根据上述方法制造的半导体结构。在本申请中公开的半导体结构及其制造方法在地层上形成应力诱导区域，其对半导体器件沟道提供有利的应力，有助于提高半导体器件的性能。

86. 发明授权

US09236384B2 Semiconductor memory device and method for accessing the same 有权
标题翻译：半导体存储器件及其访问方法
公开(公告)号：US09236384B2
公开(公告)日：2016-01-12
申请号：US14355120
申请日：2012-03-22
申请人： Zhijiong Luo , Zhengyong Zhu , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Zhengyong Zhu , Haizhou Yin , Huilong Zhu
IPC分类号： G11C11/405 , G11C5/06 , G11C5/02 , G11C7/00 , H01L27/105 , G11C11/404 , H01L29/267 , H01L29/786 , G11C8/16 , H01L27/108
CPC分类号： H01L27/1052 , G11C5/06 , G11C7/00 , G11C8/16 , G11C11/404 , G11C11/405 , H01L27/108 , H01L29/267 , H01L29/7869
摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.
摘要翻译：公开了一种半导体存储器件及其访问方法。半导体存储器件包括存储晶体管，第一控制晶体管和第二控制晶体管，其中第一控制晶体管的源电极和栅电极分别耦合到第一位线和第一字线，漏电极和第二控制晶体管的栅电极分别耦合到第二字线和第二位线，存储晶体管的栅电极耦合到第一控制晶体管的漏电极，存储晶体管的漏电极耦合到第二控制晶体管的源电极，并且存储晶体管的源电极耦合到地，并且其中存储晶体管表现出栅电极控制的存储特性。半导体存储器件增加了集成度并降低了刷新频率。

87. 发明授权

US09178070B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09178070B2
公开(公告)日：2015-11-03
申请号：US13138053
申请日：2011-03-04
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L29/786 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/42384 , H01L29/66772 , H01L29/78603
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。根据本发明的半导体结构可以通过在具有公共接触的源极区域或漏极区域之间的电容耦合来调节阈值电压，即源极接触或漏极接触，这导致简单的制造过程，更高的集成度，更低的制造成本。此外，背栅结构的非对称设计以及可以根据实际器件设计中所需而改变的背栅区域的掺杂，可以进一步增强调节阈值电压并提高器件性能的效果。

88. 发明授权

US08969930B2 Gate stack structure, semiconductor device and method for manufacturing the same 有权
标题翻译：栅叠层结构，半导体器件及其制造方法
公开(公告)号：US08969930B2
公开(公告)日：2015-03-03
申请号：US13321886
申请日：2011-04-06
申请人： Haizhoou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhoou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/28 , H01L29/66
CPC分类号： H01L21/28247 , H01L29/66545 , H01L29/78
摘要： A gate stack structure comprises an isolation dielectric layer formed on and embedded into a gate. A sidewall spacer covers opposite side faces of the isolation dielectric layer, and the isolation dielectric layer located on an active region is thicker than the isolation dielectric layer located on a connection region. A method for manufacturing the gate stack structure comprises removing part of the gate in thickness, the thickness of the removed part of the gate on the active region is greater than the thickness of the removed part of the gate on the connection region so as to expose opposite inner walls of the sidewall spacer; forming an isolation dielectric layer on the gate to cover the exposed inner walls. There is also provided a semiconductor device and a method for manufacturing the same. The methods can reduce the possibility of short-circuit occurring between the gate and the second contact hole and can be compatible with the dual-contact-hole process.
摘要翻译：栅极堆叠结构包括形成在栅极上并嵌入栅极中的隔离电介质层。侧壁间隔物覆盖隔离电介质层的相对侧面，并且位于有源区上的隔离电介质层比位于连接区上的隔离电介质层厚。一种用于制造栅极堆叠结构的方法包括去除栅极的一部分厚度，有源区上的栅极的去除部分的厚度大于连接区域上的栅极的去除部分的厚度，以便露出侧壁间隔件的相对的内壁; 在栅极上形成隔离电介质层以覆盖暴露的内壁。还提供了一种半导体器件及其制造方法。该方法可以降低栅极和第二接触孔之间发生短路的可能性，并且可以与双接触孔工艺兼容。

89. 发明授权

US08969164B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08969164B2
公开(公告)日：2015-03-03
申请号：US14002456
申请日：2012-03-23
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/08 , H01L21/84 , H01L27/12 , H01L21/8234 , H01L29/51
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/51 , H01L29/66431
摘要： A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region.
摘要翻译：半导体结构包括衬底，栅极堆叠，基极区域和源极/漏极区域，其中栅极堆叠层位于基极区域上，源极/漏极区域位于基极区域中，并且基极区域是位于基板上。在基部区域和基板之间设置支撑隔离结构，其中支撑结构的一部分连接到基板; 在基部区域和基板之间设置空腔，其中空腔由基底区域，基底和支撑隔离结构构成。在栅极堆叠的两侧，基部区域和支撑隔离结构上设置应力材料层。相应地，提供了一种用于制造这种半导体结构的方法，其抑制短沟道效应，降低寄生电容和漏电流，并且增强源/漏区的陡度。

90. 发明授权

US08828840B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08828840B2
公开(公告)日：2014-09-09
申请号：US13379546
申请日：2011-04-26
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76232 , H01L21/02381 , H01L21/02521 , H01L21/02639 , H01L21/02647
摘要： A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.
摘要翻译：公开了一种半导体器件及其制造方法。该方法包括：在第一半导体层中形成至少一个沟槽，其中沟槽的各个侧壁的至少下部部分朝向沟槽的外侧倾斜; 在沟槽中填充介电材料，使第一半导体层变薄，使得第一半导体层相对于电介质材料凹陷，并且在第一半导体层上外延生长第二半导体层，其中第一半导体层和半导体层包括彼此不同的材料。根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

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