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81. 发明授权

US08443377B2 Parallel processing system running an OS for single processors and method thereof 有权
标题翻译：并行处理系统运行单处理器的操作系统及其方法
公开(公告)号：US08443377B2
公开(公告)日：2013-05-14
申请号：US11080730
申请日：2005-03-16
申请人： Hiroaki Inoue , Junji Sakai , Tsuyoshi Abe , Masato Edahiro
发明人： Hiroaki Inoue , Junji Sakai , Tsuyoshi Abe , Masato Edahiro
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F9/544
摘要： On a parallel processing system by an OS for single processors which operates, on a multiprocessor, an OS for single processors and an existing application to realize parallel processing by the multiprocessor with respect to the application, each processor includes a communication proxy unit which transfers data between tasks spreading over the processors by proxy and the communication proxy unit on a processor in which a task on a transmission side operates holds information about an address, on a processor, of a task on a reception side to receive data transferred from the task on the transmission side as proxy for the task on the reception side.
摘要翻译：在用于单处理器的操作系统的并行处理系统中，在多处理器上操作用于单个处理器的OS和现有应用以实现多处理器相对于应用的并行处理，每个处理器包括传送数据的通信代理单元在处理器之间通过代理扩展的任务和处理器之间的通信代理单元，其中传输侧的任务在其上操作，在处理器上保存关于接收侧的任务的地址的信息，以接收从任务传送的数据发送方作为接收方的任务的代理。

82. 发明授权

US08429663B2 Allocating task groups to processor cores based on number of task allocated per core, tolerable execution time, distance between cores, core coordinates, performance and disposition pattern 有权
标题翻译：根据每个核心分配的任务数量，允许的执行时间，核心距离，核心坐标，性能和配置模式，将任务组分配到处理器核心
公开(公告)号：US08429663B2
公开(公告)日：2013-04-23
申请号：US12529367
申请日：2008-02-05
申请人： Masamichi Takagi , Masayuki Mizuno , Hiroaki Inoue
发明人： Masamichi Takagi , Masayuki Mizuno , Hiroaki Inoue
IPC分类号： G06F9/50
CPC分类号： G06F9/5027 , G06F11/1428 , G06F11/3419 , G06F11/3433 , G06F2209/483 , G06F2209/501
摘要： Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores.
摘要翻译：即使多处理器包括不均衡的性能核心，不能满足设计性能的不工作核心或核心，但是如果任务分配的设计能够满足执行应用程序的要求，则会发送多个处理器。在用于将具有多个核心的处理器分配给应用程序中的处理器执行的任务组的任务组分配方法中，计算部分测量核心的性能和配置模式，产生将测量性能以及具有指示是否可以执行应用的信息的核心的配置模式，并且参考限制条件将已经分配给核心的任务组重新分配给核心。

83. 发明授权

US08412867B2 Semiconductor integrated circuit and filter and informational delivery method using same 有权
标题翻译：半导体集成电路和滤波器及信息传递方法使用相同
公开(公告)号：US08412867B2
公开(公告)日：2013-04-02
申请号：US12663477
申请日：2008-05-30
申请人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
发明人： Hiroaki Inoue , Masamichi Takagi , Masaki Uekubo , Sunao Torii , Masato Edahiro
IPC分类号： G06F13/12 , H04L12/56
CPC分类号： G06F15/16 , G06F21/50 , G06F21/577 , H04L29/06
摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.
摘要翻译：本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

84. 发明授权

US08301936B2 Apparatus and method for performing a screening test of semiconductor integrated circuits 失效
标题翻译：用于进行半导体集成电路的屏蔽测试的装置和方法
公开(公告)号：US08301936B2
公开(公告)日：2012-10-30
申请号：US12447524
申请日：2007-10-17
申请人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
发明人： Hiroaki Inoue , Masamichi Takagi , Masayuki Mizuno
IPC分类号： G06F11/00
CPC分类号： G06F11/277
摘要： An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.
摘要翻译：公开了一种用于执行半导体集成电路的屏蔽测试的装置，所述半导体集成电路包括多个处理器，每个处理器具有用于指令执行信息的输出信号，并且所述处理器可编程地可操作。用于执行半导体集成电路的屏蔽测试的装置包括：指令/数据信号同步电路，用于将指令的提供同步到所述各个处理器并用于同步向所述各个处理器提供数据; 以及跟踪比较电路，用于比较从各个处理器输出的指令执行信息，以确定所述处理器中的任何一个是否输出了不同的指令执行信息。

85. 发明授权

US08293557B2 Manufacturing method of MEMS device, and substrate used therefor 失效
标题翻译： MEMS器件的制造方法及其使用的衬底
公开(公告)号：US08293557B2
公开(公告)日：2012-10-23
申请号：US13012104
申请日：2011-01-24
申请人： Hiroaki Inoue , Tadashi Nakatani , Satoshi Ueda
发明人： Hiroaki Inoue , Tadashi Nakatani , Satoshi Ueda
IPC分类号： H01L21/00
CPC分类号： H01H59/0009 , Y10T428/24521 , Y10T428/24562
摘要： A method for manufacturing a MEMS device, includes: preparing a substrate provided with a first substrate in which a cavity is formed, and a second substrate that is bonded to a side of the first substrate on which the cavity is formed and includes a slit to delimit a movable portion in a position corresponding to the cavity, the second substrate, including a first surface thereof facing the first substrate, being provided with a thermally-oxidized film selectively formed on the first surface in a position corresponding to the movable portion; forming a first electrode layer on a second surface opposite to the first surface on which the thermally-oxidized film for the movable portion is formed; forming a sacrifice layer on the first electrode layer and the second substrate; forming a second electrode layer on the sacrifice layer; and removing the sacrifice layer and the thermally-oxidized film after the second electrode layer is formed.
摘要翻译：一种MEMS器件的制造方法，包括：准备具有形成有空腔的第一基板的基板和与形成有所述空腔的所述第一基板的一侧接合的第二基板，所述第二基板具有狭缝，在与空腔相对应的位置限定可移动部分，所述第二基板包括其面向所述第一基板的第一表面，所述第二基板具有在对应于所述可动部分的位置中选择性地形成在所述第一表面上的热氧化膜; 在形成有用于可动部分的热氧化膜的第一表面相对的第二表面上形成第一电极层; 在所述第一电极层和所述第二基板上形成牺牲层; 在牺牲层上形成第二电极层; 并且在形成第二电极层之后去除牺牲层和热氧化膜。

86. 发明授权

US08289723B2 Method of fabricating packaged-device 有权
标题翻译：制造包装装置的方法
公开(公告)号：US08289723B2
公开(公告)日：2012-10-16
申请号：US12458604
申请日：2009-07-16
申请人： Hiroaki Inoue , Takashi Katsuki , Fumihiko Nakazawa
发明人： Hiroaki Inoue , Takashi Katsuki , Fumihiko Nakazawa
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： G01P15/125 , B81C1/00301 , G01C19/5719 , G01P1/023 , G01P15/0802 , H01L21/76898 , H01L23/481 , H01L2924/0002 , Y10T29/49128 , H01L2924/00
摘要： A method includes forming grooves in first regions included in a first wafer to form wiring regions defined by the grooves; forming insulating portions in the grooves; joining a surface of the first wafer on which the wiring regions are formed to a first surface of a device wafer including device forming regions after forming the insulating portions; forming through holes in the wiring regions of the first wafer after joining the first wafer to the device wafer, the holes extending through the first wafer; filling the holes with a conductive material; joining a second wafer to a second surface of the device wafer opposite the first surface, the second wafer including second regions; exposing the wiring regions by thinning the first wafer after joining the first wafer to the device wafer; and cutting the device wafer, the first wafer, and the second wafer after thinning the first wafer.
摘要翻译：一种方法包括在包括在第一晶片中的第一区域中形成凹槽以形成由凹槽限定的布线区域; 在槽中形成绝缘部分; 在形成有所述布线区域的所述第一晶片的表面之后，在形成所述绝缘部分之后，将包括器件形成区域的器件晶片的第一表面接合; 在将所述第一晶片连接到所述器件晶片之后，在所述第一晶片的布线区域中形成通孔，所述孔延伸穿过所述第一晶片; 用导电材料填充孔; 将第二晶片连接到与所述第一表面相对的所述器件晶片的第二表面，所述第二晶片包括第二区域; 在将第一晶片连接到器件晶片之后，通过使第一晶片变薄来暴露布线区域; 以及在使所述第一晶片变薄之后切割所述器件晶片，所述第一晶片和所述第二晶片。

87. 发明授权

US08248073B2 Semiconductor integrated circuit and testing method therefor 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US08248073B2
公开(公告)日：2012-08-21
申请号：US12529458
申请日：2008-02-19
申请人： Hiroaki Inoue , Masamichi Takagi
发明人： Hiroaki Inoue , Masamichi Takagi
IPC分类号： G01V3/00
CPC分类号： G01R31/31724 , G01R31/31723 , G01R31/318536 , G06F11/2236
摘要： A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection network (1000) and which issues a test control request associated with the test of the core (99) via the inter-connection network (1000). The inter-connection network (1000) is constituted of a plurality of adapters (3000) which serve as connection interfaces of the plurality of cores (99) and the test controller (500), respectively, and a plurality of routers (2000) which connect the plurality of adapters (3000). The adapters (3000) connected with the core (99) comprise a core testing unit for vicariously testing core (99) connected to itself based on the test control request received from the test controller (500) via the inter-connection network (1000).
摘要翻译：半导体集成电路包括与互连网络（1000）连接的多个核（99）和与所述互连网络（1000）连接的测试控制器（500），并且发出与通过互连网络（1000）对核心（99）进行测试。互连网络（1000）由分别用作多个核（99）和测试控制器（500）的连接接口的多个适配器（3000）和多个路由器（2000）组成，多个路由器连接多个适配器（3000）。与核心（99）连接的适配器（3000）包括核心测试单元，用于根据从测试控制器（500）经由互连网络（1000）接收的测试控制请求代替连接到其自身的核心（99）。

88. 发明申请

US20120202889A1 PRODUCTION METHOD FOR ASTAXANTHIN-CONTAINING COMPOSITION 审中-公开
标题翻译：含阿斯沙星含量组合物的生产方法
公开(公告)号：US20120202889A1
公开(公告)日：2012-08-09
申请号：US13389924
申请日：2010-08-11
申请人： Hiroaki Inoue , Noriyuki Kizaki , Hirokazu Nanba
发明人： Hiroaki Inoue , Noriyuki Kizaki , Hirokazu Nanba
IPC分类号： A61K31/122 , C07C45/78 , A23K1/16 , C12N1/14 , C12N1/12 , A23K1/18 , C12N1/16 , C12N1/20
CPC分类号： A61K31/01 , A23K20/174 , A23K20/179 , A61K31/122 , C12P23/00
摘要： The present invention relates to a method for reducing the relative ratio of 3-hydroxy-3′,4′-didehydro- β, Ψ-caroten-4-one (HDCO) to astaxanthin in a composition containing astaxanthin and HDCO by contacting the composition with an acidic medium having a pH of 3 or less and/or a basic medium having a pH of 9 or greater, and also relates to a method for producing an astaxanthin-containing composition which includes reducing the relative ratio of HDCO by the above method. By means of the method of the present invention, the relative ratio of HDCO, the biological function of which is not known, in an astaxanthin-containing composition can be easily reduced.
摘要翻译：本发明涉及一种降低含有虾青素和HDCO的组合物中3-羟基-3'，4'-二脱氢糠醛，Ψ-胡萝卜素-4-酮（HDCO）与虾青素的相对比例的方法， pH为3以下的酸性介质和/或pH为9以上的碱性介质的组合物，还涉及含有虾青素的组合物的制造方法，其包括降低HDCO与上述相对的比例方法。通过本发明的方法，可以容易地降低含有虾青素的组合物中HDCO（其生物学功能不知道）的相对比例。

89. 发明申请

US20120166721A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND CACHE DEVICE 有权
标题翻译：半导体集成电路装置，控制半导体集成电路装置的方法和缓存装置
公开(公告)号：US20120166721A1
公开(公告)日：2012-06-28
申请号：US13393814
申请日：2010-08-18
申请人： Hiroaki Inoue
发明人： Hiroaki Inoue
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0802 , G06F2212/1028 , Y02D10/13
摘要： There are provided a semiconductor integrated circuit device, a method of controlling a semiconductor integrated circuit device, and a cache device capable of efficiently implementing power saving, wherein the cache device includes a low-voltage operation enabling cache (200), and a small-area cache (300) having a type different from that of the cache (200), the cache (200) and the cache (300) being independently supplied with source voltage; the cache (200) being operable at a voltage lower than the lower limit voltage at which the cache (300) is operable; a cache control unit (400) operating switchable controls between a first mode allowing only the cache (200) to operate, and a second mode allowing the cache (200) or the cache (300) to operate; and the cache (200) in the first mode operating to supply a voltage below the lower limit voltage at which the cache (300) is operable, while interrupting power supply to the cache (300).
摘要翻译：提供了一种半导体集成电路器件，一种半导体集成电路器件的控制方法和能够有效地实现功率节省的高速缓存器件，其中该高速缓存器件包括一个使能高速缓存（200）的低压工作，区域缓存（300）具有与高速缓存（200）不同的类型，高速缓存（200）和高速缓存（300）被独立地提供源电压; 高速缓存（200）可操作在低于高速缓存（300）可操作的下限电压的电压; 高速缓存控制单元（400）在允许仅高速缓存（200）操作的第一模式和允许高速缓存（200）或高速缓存（300）操作的第二模式之间操作可切换控制; 以及在所述第一模式下的所述高速缓存（200）工作以提供低于所述高速缓存（300）可操作的所述下限电压的电压，同时中断向所述高速缓存（300）的电力供应。

90. 发明申请

US20120030377A1 INFORMATION PROCESSING SYSTEM, INFORMATION COMPRESSION DEVICE, INFORMATION DECOMPRESSION DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM 有权
标题翻译：信息处理系统，信息压缩设备，信息分解设备，信息处理方法和程序
公开(公告)号：US20120030377A1
公开(公告)日：2012-02-02
申请号：US13262181
申请日：2010-03-19
申请人： Hiroaki Inoue
发明人： Hiroaki Inoue
IPC分类号： G06F15/16
CPC分类号： H03M7/30 , G11C7/103 , G11C29/003 , H04L29/12311
摘要： In order to improve the compression rate for configuration information including address information and data information when transmitting or storing configuration information which includes addresses and data having differing characteristics, an information compression device is provided with a compressor which receives as input and compresses the configuration information provided with the addresses and data, and a compressed information storage module for storing the configuration information which is compressed, that is, compressed configuration information, as the information to be decompressed for the user, said compressor including an information separating module for separating the configuration information into address information and data information, an address compressor and data compressor which separately compress the separated address information and data information, and a compressed information outputting module for combining the compressed address information and data information and outputting the result as compressed configuration information.
摘要翻译：为了在发送或存储具有不同特征的地址和数据的配置信息的情况下提高包括地址信息和数据信息的配置信息的压缩率，信息压缩装置设置有作为输入接收并压缩提供的配置信息的压缩器具有地址和数据的压缩信息存储模块，以及用于将被压缩的配置信息（即，压缩配置信息）存储为要为用户解压缩的信息的压缩信息存储模块，所述压缩器包括用于分离配置信息的信息分离模块地址信息和数据信息，分离地压缩分离的地址信息和数据信息的地址压缩器和数据压缩器，以及压缩信息输出模块，用于将压缩的地址信息和数据信息并将结果作为压缩配置信息输出。

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