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81. 发明授权

US08466991B2 Optical black pixel cell readout systems and methods 有权
标题翻译：光学黑色像素单元读出系统及方法
公开(公告)号：US08466991B2
公开(公告)日：2013-06-18
申请号：US12838705
申请日：2010-07-19
申请人： Yaowu Mo , Chen Xu , Yandong Chen
发明人： Yaowu Mo , Chen Xu , Yandong Chen
IPC分类号： H04N9/64 , H04N5/335
CPC分类号： H04N5/347 , H04N5/361 , H04N5/378
摘要： This is generally directed to systems and methods for reading optical black pixel cells. For example, in some embodiments, the columns of a pixel array can be shunted together during an optical black pixel readout phase of the imaging system. This may, for example, help improve correction of column fixed pattern noise or other noise. In some embodiments, the column may be shunted together during the optical black pixel readout phase of the imaging system and not shunted during other phases of the imaging system (e.g., when reading values from active pixel cells, barrier pixel cells, etc). In some embodiments, circuitry for providing the column shunting can be implemented as an independent block of the imaging system. In other embodiments, this circuitry can be implemented within other blocks of the imaging system. As an illustration, the shunting circuitry can be implemented within a VLN block of the imaging system.
摘要翻译：这通常涉及用于读取光学黑色像素单元的系统和方法。例如，在一些实施例中，像素阵列的列可以在成像系统的光学黑色像素读出阶段期间被分流在一起。这可以例如有助于改进列固定模式噪声或其他噪声的校正。在一些实施例中，在成像系统的光学黑色像素读出阶段期间，列可以被分流在一起，并且在成像系统的其它阶段（例如当从有源像素单元，障碍像素单元等读取值时）不被分流。在一些实施例中，用于提供列分流的电路可以被实现为成像系统的独立块。在其他实施例中，该电路可以在成像系统的其他块内实现。作为说明，分流电路可以在成像系统的VLN块内实现。

82. 发明授权

US08466263B2 Carbonic anhydrase IX (G250) anitbodies 有权
标题翻译：碳酸酐酶IX（G250）活性
公开(公告)号：US08466263B2
公开(公告)日：2013-06-18
申请号：US12095773
申请日：2006-12-04
申请人： Wayne A. Marasco , Agnes Lo , Chen Xu
发明人： Wayne A. Marasco , Agnes Lo , Chen Xu
IPC分类号： C07K16/40 , C07K16/00 , A61K39/395
CPC分类号： C07K16/40 , A61K38/2013 , A61K39/3955 , A61K51/1045 , A61K51/1075 , A61K2039/505 , C07K16/30 , C07K2317/21 , C07K2317/565 , C07K2317/622 , C07K2317/73 , C07K2317/76
摘要： The invention provides scFv antibodies and monoclonal antibodies that bind to and decrease an activity of Carbonic Anhydrase IX (G250). Also provided are methods of treating and/or preventing cancer, such as renal clear cell cancer. Also provided are methods of identifying a carbonic anhydrase IX (G250) protein. The invention additionally provides methods of modifying immune effector cells, and the immune effector cells modified thereby.
摘要翻译：本发明提供结合并降低碳酸酐酶IX（G250）的活性的scFv抗体和单克隆抗体。还提供了治疗和/或预防癌症的方法，例如肾透明细胞癌。还提供了鉴定碳酸酐酶IX（G250）蛋白质的方法。本发明另外提供了修饰免疫效应细胞和由此修饰的免疫效应细胞的方法。

83. 发明授权

US08458641B2 Method, system, and design structure for making voltage environment consistent for reused sub modules in chip design 有权
标题翻译：芯片设计中重用子模块的电压环境一致的方法，系统和设计结构
公开(公告)号：US08458641B2
公开(公告)日：2013-06-04
申请号：US13031754
申请日：2011-02-22
申请人： Xiao Feng Tang , Chen Xu , Jia Lian Tang , Xia Li
发明人： Xiao Feng Tang , Chen Xu , Jia Lian Tang , Xia Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/66 , G06F2217/78
摘要： The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period.
摘要翻译：本发明公开了一种用于使芯片设计中的重用子模块的电压环境一致的方法，系统和设计结构，其中每个重复使用的子模块通过电源环上的电源连接点连接到芯片的电网模块，所述方法包括：调整多个重用子模块的电力连接点的数量和位置，使得所述多个重用子模块中的电力连接点的数量和对应的电力连接点的位置相同; 调整所述电力网上连接有所述电力连接点的所述多个再利用子模块的电力线，使得所述多个重复使用的子模块中相应的电力连接点的电压一致。本发明可以减少芯片设计中重用子模块的时序变化，最终实现降低设计复杂度和工作负载并缩短设计周期的目标。

84. 发明授权

US08453085B2 Method for estimating the latency time of a clock tree in an ASIC design 失效
标题翻译：估计ASIC设计中时钟树的延迟时间的方法
公开(公告)号：US08453085B2
公开(公告)日：2013-05-28
申请号：US13031953
申请日：2011-02-22
申请人： Liang Ge , Gong Qiong Li , Suo Ming Pu , Chen Xu
发明人： Liang Ge , Gong Qiong Li , Suo Ming Pu , Chen Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62 , G06F2217/84
摘要： Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.
摘要翻译：估计ASIC的时钟树的延迟时间，包括：提供与ASIC的时钟树相关的网表和布局; 根据与时钟树相关联的网表提取由时钟树连接的多个负载定时设备; 根据与时钟树相关的位置提取由时钟树连接的负载定时设备的物理分配区域; 根据负载定时装置的数量，负载定时装置的物理分配面积和与ASIC设计有关的设计数据中的时钟树的延迟时间之间的关系来估计时钟树的等待时间。

85. 发明授权

US08368792B2 Imager methods, apparatuses, and systems providing a skip mode with a wide dynamic range operation 有权
公开(公告)号：US08368792B2
公开(公告)日：2013-02-05
申请号：US13097279
申请日：2011-04-29
申请人： Chen Xu
发明人： Chen Xu
IPC分类号： H04N3/14 , H04N5/335 , H04N1/04
CPC分类号： H04N5/3456 , H04N5/23245 , H04N5/335 , H04N5/3458 , H04N5/3532 , H04N5/3535 , H04N5/35581 , H04N5/3742 , H04N9/045
摘要： Methods, apparatuses and systems provide a high dynamic range mode of operation for an image sensor when operating in a skip mode where certain pixels of an array are not readout. Multiple integration periods are employed in the skip mode with selected pixels being readout through circuits associated with pixels that are not readout.

86. 发明授权

US08324548B2 Imaging devices and methods for charge transfer 有权
标题翻译：成像设备和电荷转移方法
公开(公告)号：US08324548B2
公开(公告)日：2012-12-04
申请号：US12412120
申请日：2009-03-26
申请人： Yaowu Mo , Chen Xu
发明人： Yaowu Mo , Chen Xu
IPC分类号： H01J40/14
CPC分类号： H03F3/08
摘要： A pixel circuit having improved charge transfer including an amplifier having an input node electrically connected to a charge storage node of the pixel circuit, and a negative feedback control loop having a capacitance element electrically connected between the input node and an output node of said amplifier.
摘要翻译：一种具有改进的电荷转移的像素电路，包括具有电连接到像素电路的电荷存储节点的输入节点的放大器，以及具有电连接在所述放大器的输入节点和输出节点之间的电容元件的负反馈控制环路。

87. 发明申请

US20120119317A1 ANTIBLOOMING IMAGING APPARATUS, SYSTEMS, AND METHODS 有权
标题翻译：防止成像设备，系统和方法
公开(公告)号：US20120119317A1
公开(公告)日：2012-05-17
申请号：US13351106
申请日：2012-01-16
申请人： Chen Xu , Gennadiy Agranov , Igor Karasev
发明人： Chen Xu , Gennadiy Agranov , Igor Karasev
IPC分类号： H01L27/144
CPC分类号： H04N5/378 , H04N5/3594 , H04N5/3745
摘要： Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.
摘要翻译：描述了装置，系统和方法以帮助减少有源像素传感器中的暗电流。在各种实施例中，势垒布置被配置为阻挡在感光区域外部产生的电荷载流子的流动。在各种实施例中，形成势阱势垒布置，以在积分时间期间使电荷载流子远离光敏区域。

88. 发明申请

US20120110541A1 CONSTRAINT OPTIMIZATION OF SUB-NET LEVEL ROUTING IN ASIC DESIGN 有权
标题翻译： ASIC设计中子网路由优化的约束优化
公开(公告)号：US20120110541A1
公开(公告)日：2012-05-03
申请号：US13280146
申请日：2011-10-24
申请人： Liang Ge , Xia Li , Jia Lian Tang , Xiao Feng Tang , Chen Xu
发明人： Liang Ge , Xia Li , Jia Lian Tang , Xiao Feng Tang , Chen Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5031 , G06F2217/84
摘要： Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds.
摘要翻译：可以实现功能，以优化集成电路设计中的连接约束。确定与集成电路的多个子连接中的第一个相关联的目标定时路径。至少部分地基于与多个子连接中的第一个相关联的目标定时路径来确定与多个子连接中的第一个子连接相关联的定时概率值和路线概率值。定时概率值表示在目标定时路径上满足定时闭合的概率。路由概率值指示与多个子连接中的第一个相关联的目标定时路径上的物理路由轨迹解决拥塞的概率。与多个子连接中的第一个连接相关联的当前连接约束根据多个子连接中的第一个子连接对应的连接约束模型进行修改。

89. 发明申请

US20120047478A1 Method For Estimating The Latency Time Of A Clock Tree In An Asic Design 失效
标题翻译：用于估计Asic设计中时钟树的延迟时间的方法
公开(公告)号：US20120047478A1
公开(公告)日：2012-02-23
申请号：US13031953
申请日：2011-02-22
申请人： Liang Ge , Gong Qiong Li , Suo Ming Pu , Chen Xu
发明人： Liang Ge , Gong Qiong Li , Suo Ming Pu , Chen Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62 , G06F2217/84
摘要： Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.
摘要翻译：估计ASIC的时钟树的延迟时间，包括：提供与ASIC的时钟树相关的网表和布局; 根据与时钟树相关联的网表提取由时钟树连接的多个负载定时设备; 根据与时钟树相关的位置提取由时钟树连接的负载定时设备的物理分配区域; 根据负载定时装置的数量，负载定时装置的物理分配面积和与ASIC设计有关的设计数据中的时钟树的延迟时间之间的关系来估计时钟树的等待时间。

90. 发明授权

US08114718B2 Antiblooming imaging apparatus, systems, and methods 有权
公开(公告)号：US08114718B2
公开(公告)日：2012-02-14
申请号：US12719562
申请日：2010-03-08
申请人： Chen Xu , Gennadiy Agranov , Igor Karasev
发明人： Chen Xu , Gennadiy Agranov , Igor Karasev
IPC分类号： H01L21/339
CPC分类号： H04N5/378 , H04N5/3594 , H04N5/3745
摘要： Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.

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