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    • 87. 发明授权
    • Disk drive using seek profile to enhance fly height control
    • 磁盘驱动器使用查找配置文件来增强飞行高度控制
    • US06687081B1
    • 2004-02-03
    • US09570799
    • 2000-05-15
    • Matthew O'HaraDon BrunnetYu SunDavid M. Sigmond
    • Matthew O'HaraDon BrunnetYu SunDavid M. Sigmond
    • G11B5596
    • G11B5/5547G11B5/5534G11B5/6011
    • A disk drive uses seek profile manipulation to provide enhanced transducer fly height control. The maximum seek velocity that is used during a seek operation is made dependent upon, among other things, the direction associated with the seek operation (i.e., either radially inward or radially outward with respect to the disk). In a preferred embodiment, the maximum seek velocity in a direction that normally results in a fly height loss is made less than the maximum seek velocity in the opposite direction. Thus, a minimum transducer fly height can be maintained with minimal effect on average seek time in the disk drive. In one approach, the maximum seek velocity values are stored within a lookup table within the disk drive.
    • 磁盘驱动器使用查找配置文件操作来提供增强的换能器飞行高度控制。 在搜索操作期间使用的最大寻道速度取决于除了别的以外与寻道操作相关联的方向(即,相对于盘径向向内或径向向外)。 在优选实施例中,使通常导致飞高高度损失的方向上的最大寻道速度小于相反方向上的最大寻道速度。 因此,可以保持最小的传感器飞行高度,对磁盘驱动器中的平均寻道时间影响最小。 在一种方法中,最大寻道速度值存储在磁盘驱动器内的查找表中。
    • 88. 发明授权
    • Method of fabricating double densed core gates in sonos flash memory
    • 在sonos闪存中制造双激光核心门的方法
    • US06630384B1
    • 2003-10-07
    • US09971483
    • 2001-10-05
    • Yu SunMichael A. Van BuskirkMark T. Ramsbey
    • Yu SunMichael A. Van BuskirkMark T. Ramsbey
    • H01L21336
    • H01L27/11568H01L27/115
    • One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.
    • 本发明的一个方面涉及一种形成非易失性半导体存储器件的方法,包括在衬底上形成电荷俘获电介质,所述衬底具有芯区域和外围区域; 在芯区域中的电荷俘获电介质上形成第一组存储单元栅极; 在所述第一组存储单元栅极周围形成保形绝缘材料层; 以及在所述核心区域中形成第二组存储器单元栅极,其中所述第二组存储单元栅极的每个存储单元栅极与所述第一组存储单元栅极的至少一个存储单元栅极相邻, 第一组存储单元栅极与第二组存储单元栅极的至少一个存储单元栅极相邻,并且保形绝缘材料层位于每个相邻的存储单元栅极之间。
    • 89. 发明授权
    • Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices
    • 在非易失性存储器半导体器件中形成浮置栅极的方法和装置
    • US06274433B1
    • 2001-08-14
    • US09476121
    • 2000-01-03
    • Mark RamsbeyTuan D. PhamYu SunKenneth W. Au
    • Mark RamsbeyTuan D. PhamYu SunKenneth W. Au
    • H01L218247
    • H01L27/11521H01L27/115H01L29/42324
    • Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
    • 提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。 通过有利地减小浮动栅极的厚度,这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。 改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。 控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。 裂纹通常发生在半导体器件的随后热处理期间。 因此,所公开的方法和布置防止了控制栅极上的硅化物层的破裂,这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。