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81. 发明授权

US07579875B2 Interface circuit and control method thereof 有权
标题翻译：接口电路及其控制方法
公开(公告)号：US07579875B2
公开(公告)日：2009-08-25
申请号：US11542149
申请日：2006-10-04
申请人： Yoshiharu Kato
发明人： Yoshiharu Kato
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/0175
摘要： This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal attains an inactive state. The interface circuit has a comparing portion for comparing the potential of the DQS with a threshold potential VREFH which is a potential that is different from the intermediate potential VM.
摘要翻译：本发明提供一种用于检测来自DDR SDRAM的DQS信号处于中间电位的接口电路。接口电路至少连接到从DDR SDRAM发送DQS信号的信号线，并且当信号达到非活动状态时到达中间电位VM。接口电路具有比较部分，用于将DQS的电位与作为不同于中间电位VM的电位的阈值电位VREFH进行比较。

82. 发明授权

US07388791B2 Signal interface 有权
标题翻译：信号接口
公开(公告)号：US07388791B2
公开(公告)日：2008-06-17
申请号：US11583130
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： G11C7/10
CPC分类号： H04L25/0282 , H04L5/04 , H04L25/0294
摘要： Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.
摘要翻译：多个发射机单元分别产生对应于多个逻辑值的多个电流，并将电流传播到公共信号线。公共信号线合成由发射机单元产生的电流，并将其作为合成电流传播到接收机单元。接收器单元根据合成电流恢复发射机单元产生的逻辑值。发射机单元对应于逻辑值产生的电流值各自不同，使得可以针对逻辑值的每个组合来改变合成电流的值。因此，接收机单元可以基于合成电流来恢复从各个发射机单元输出的逻辑值。也就是说，采用公共信号线使得能够同时接收从发送单元发送的信号。因此，放置在发射机单元和接收机单元之间的信号线的数量减少。

83. 发明授权

US07382419B2 Liquid crystal television and liquid crystal display apparatus 失效
标题翻译：液晶电视和液晶显示装置
公开(公告)号：US07382419B2
公开(公告)日：2008-06-03
申请号：US11166469
申请日：2005-06-23
申请人： Yoshiharu Kato
发明人： Yoshiharu Kato
IPC分类号： H04N5/64
CPC分类号： H04N5/64 , F16M11/10 , F16M11/2014 , F16M2200/08
摘要： A liquid crystal display apparatus including a tilt mechanism, which is capable of preventing an inadvertent insertion of a finger of a user in a groove of a bracket of the tilt mechanism even while a cover for concealing the bracket is removed, wherein provided is a washer-like member or inadvertent-insertion preventer which has a through-hole or perforated portion through which a pawl formed in a mainbody bracket or one of two brackets is inserted, and is attached to the pawl at a position to contact a stand bracket or the other of the two brackets, by inserting the pawl through the through-hole. The washer-like member is preferably made of a plastic and sandwiched between the two brackets.
摘要翻译：一种液晶显示装置，包括倾斜机构，其能够防止用户的手指无意插入倾斜机构的支架的凹槽中，即使在用于隐藏托架的盖子被移除时，其中设置有垫圈其具有通孔或穿孔部分，通过该通孔或穿孔部分形成在主体托架中的棘爪或两个托架中的一个托架中的棘爪，并且在与支架支架或者支架支架接触的位置处附接到棘爪通过将棘爪插入通孔中，两个支架中的另一个。垫圈状构件优选地由塑料制成并夹在两个托架之间。

84. 发明授权

US07362649B2 Memory control device and memory control method 有权
标题翻译：内存控制装置和内存控制方式
公开(公告)号：US07362649B2
公开(公告)日：2008-04-22
申请号：US11640906
申请日：2006-12-19
申请人： Yoshiharu Kato
发明人： Yoshiharu Kato
IPC分类号： G11C8/00
CPC分类号： G11C5/06
摘要： There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a select circuit 27 is changed by a switch signal SWS2. In this case, the changeover is made so that a select signal S2 outputted from an internal circuit 40 is inputted to a predetermined memory terminal of the memory chip CC2. The select signal S2 is inputted to the corresponding predetermined memory terminal of the memory chip CC2, and thereby, the memory chip CC2 is activated, and set to a state capable of inputting and outputting control signals 21 to 25. The control signals 21 to 25 are assigned to control terminals P21 to P27 after being hanged by the select circuit 27 in signal sequence corresponding to terminal array sequence of memory terminals 21a to 27a of the memory chip CC2.
摘要翻译：提供了存储器控制装置和存储器控制方法，可以防止多条交叉布线的布线复杂化，降低产量和质量。当存储器控制装置CC 1选择存储器芯片CC 2时，选择电路27的内部电路被切换信号SWS2改变。在这种情况下，进行切换，使得从内部输出的选择信号S 2 电路40被输入到存储器芯片CC 2的预定存储器端子。选择信号S 2被输入到存储器芯片CC 2的对应的预定存储器端子，由此存储器芯片CC 2被激活，并被设置为一个能够输入和输出控制信号21至25的状态。控制信号21至25被分配给控制端P21至P27，在选择电路27以对应于存储器端子21a的端子阵列序列的信号序列到27位的内存芯片CC 2。

85. 发明授权

US07245549B2 Semiconductor memory device and method of controlling the semiconductor memory device 有权
标题翻译：半导体存储器件和控制半导体存储器件的方法
公开(公告)号：US07245549B2
公开(公告)日：2007-07-17
申请号：US11058302
申请日：2005-02-16
申请人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
发明人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C8/00
CPC分类号： G11C11/4094 , G11C11/4076 , G11C2207/005
摘要： A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.
摘要翻译：提供一种半导体存储装置及其控制方法，其可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。此外，根据感测放大电源线和位线的布线容量分量，通过更高的电压电平来驱动均衡电容分量较高的布线的电路。

86. 发明申请

US20070159906A1 Semiconductor memory device, refresh control method thereof, and test method thereof 失效
标题翻译：半导体存储器件，其刷新控制方法及其测试方法
公开(公告)号：US20070159906A1
公开(公告)日：2007-07-12
申请号：US11715452
申请日：2007-03-08
申请人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
发明人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C29/50016 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/028 , G11C29/50 , G11C29/783 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.
摘要翻译：本发明提供一种由于适当的刷新稀疏功能而在待机状态下减少电流消耗的半导体存储器件及其刷新控制方法。当刷新操作和外部访问操作彼此独立地执行时添加刷新稀疏功能时，刷新地址计数器输出刷新地址Add（C）并将预定的高位比特输入到刷新 - 作为高阶刷新地址的输出控制Add（C）（m），其中进行关于刷新操作的判断。与判断结果相对应的刷新允许信号RFEN被输入到字驱动器以激活和控制字驱动器。刷新稀疏控制电路的判断处理可嵌入行系统的访问时间。

87. 发明授权

US07158437B2 Memory control device and memory control method 有权
标题翻译：内存控制装置和内存控制方式
公开(公告)号：US07158437B2
公开(公告)日：2007-01-02
申请号：US10850113
申请日：2004-05-21
申请人： Yoshiharu Kato
发明人： Yoshiharu Kato
IPC分类号： G11C8/00
CPC分类号： G11C5/06
摘要： There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a select circuit 27 is changed by a switch signal SWS2. In this case, the changeover is made so that a select signal S2 outputted from an internal circuit 40 is inputted to a predetermined memory terminal of the memory chip CC2. The select signal S2 is inputted to the corresponding predetermined memory terminal of the memory chip CC2, and thereby, the memory chip CC2 is activated, and set to a state capable of inputting and outputting control signals 21 to 25. The control signals 21 to 25 are assigned to control terminals P21 to P27 after being hanged by the select circuit 27 in signal sequence corresponding to terminal array sequence of memory terminals 21a to 27a of the memory chip CC2.
摘要翻译：提供了存储器控制装置和存储器控制方法，可以防止多条交叉布线的布线复杂化，降低产量和质量。当存储器控制装置CC 1选择存储器芯片CC 2时，选择电路27的内部电路被切换信号SWS 2改变。在这种情况下，进行切换，使得从内部电路40输出的选择信号S 2被输入到存储芯片CC 2的预定存储器端子。选择信号S 2被输入到存储器芯片CC 2的对应的预定存储器端子，从而使存储器芯片CC 2被激活，并被设置为能够输入和输出控制信号21至25的状态。控制信号21至25被分配给选择电路27以对应于存储器芯片CC 2的存储器端子21a至27a的端子阵列序列的信号序列挂起之后的控制端子P21至P27。

88. 发明授权

US07142468B2 Control method of semiconductor memory device and semiconductor memory device 有权
标题翻译：半导体存储器件和半导体存储器件的控制方法
公开(公告)号：US07142468B2
公开(公告)日：2006-11-28
申请号：US10299713
申请日：2002-11-20
申请人： Yoshiharu Kato , Satoru Kawamoto
发明人： Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4094 , G11C7/12 , G11C11/4076 , G11C11/4085 , G11C2207/2281
摘要： It is intended to provide a control method of a semiconductor memory device and a semiconductor memory device capable of shortening pre-charge operation time that comes after termination of successive data access operation, namely, successive data read/write operation, without causing deterioration of restore voltage to memory cells and delay of initial data access time. An activated word line WL0 is deactivated with appropriate timing that is between time after bit line pairs (BL0 and /BL0, . . . BLN and /BLN) are differentially amplified up to full amplitude voltage level and time where column selecting lines CL0, . . . CLN are selected. That is, deactivation time τA for the word line can be embedded in a period of successive data access operation. Pre-charge operation can be terminated within time that is a sum of deactivation time τB of a sense amplifier and equalizing time τC of the bit line pairs. Thereby, pre-charge period can be shortened.
摘要翻译：旨在提供一种半导体存储器件和半导体存储器件的控制方法，其能够缩短在连续的数据存取操作结束后即连续的数据读/写操作而导致的预充电操作时间，而不会导致恢复的恶化对存储单元的电压和初始数据存取时间的延迟。激活字线WL 0被禁用，其中位置线对（BL 0和/ BL 0，... BLN和/ BLN）之间的时间之间的适当定时被差分放大到全幅度电压电平，并且列选择线 CL 0，。。。选择CLN。也就是说，字线的去激活时间τA可以嵌入在连续数据访问操作的时段中。可以在时间内终止预充电操作，该时间是读出放大器的去激活时间τB和位线对的均衡时间tauC之和。从而可以缩短预充电期间。

89. 发明申请

US20060028893A1 Semiconductor memory device, refresh control method thereof, and test method thereof 有权
公开(公告)号：US20060028893A1
公开(公告)日：2006-02-09
申请号：US11249454
申请日：2005-10-14
申请人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
发明人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
IPC分类号： G11C7/00
CPC分类号： G11C29/50016 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/028 , G11C29/50 , G11C29/783 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

90. 发明授权

US06862237B2 Data access method of semiconductor memory device and semiconductor memory device 失效
标题翻译：半导体存储器件和半导体存储器件的数据存取方法
公开(公告)号：US06862237B2
公开(公告)日：2005-03-01
申请号：US10261951
申请日：2002-10-02
申请人： Yoshiharu Kato
发明人： Yoshiharu Kato
IPC分类号： G11C7/08 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C7/00
CPC分类号： G11C11/4076 , G11C11/406
摘要： In the case that a refresh operation is carried out which is independent from an external access operation, both a data access method of a semiconductor memory device, and a semiconductor memory device are provided by which time suitable of each of these external access operation and refresh operation is set. While a time-measuring start signal “SIN” is entered into a path switching means, the path switching means is connected to either a first timer section or a second timer section under control of an external-access-operation-start-request signal REQ(O) and a refresh-operation-start-request signal REQ(I). Both the first and second timer sections measure both time “τO” and time “τI” to output a time-measuring stop signal “SOUT.” The measuring time “τO” corresponds to differential amplification time of a bit line pair when the external access operation is carried out, whereas the measuring time “τI” corresponds to differential amplification time when the refresh operation is carried out. Alternatively, the measuring time “τO” may be varied by reading/writing operations so as to be set. As a consequence, proper amplification time can be set every operation mode.
摘要翻译：在执行独立于外部访问操作的刷新操作的情况下，提供半导体存储器件的数据存取方法和半导体存储器件，其中适合这些外部访问操作和刷新操作设置。当时间测量开始信号“SIN”被输入到路径切换装置中时，路径切换装置在外部访问操作启动请求信号REQ的控制下连接到第一定时器部分或第二定时器部分（O）和刷新操作开始请求信号REQ（I）。第一和第二计时器部分同时测量时间“tauO”和时间“tauI”，以输出时间测量停止信号“SOUT”。当执行外部访问操作时，测量时间“tauO”对应于位线对的差分放大时间，而测量时间“τI”对应于执行刷新操作时的差分放大时间。或者，测量时间“τ0”可以通过读/写操作来改变以被设定。因此，可以在每个操作模式下设置适当的放大时间。

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