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    • 83. 发明授权
    • Loadless static random access memory device and method of manufacturing same
    • 无负载静态随机存取存储器件及其制造方法
    • US06455904B1
    • 2002-09-24
    • US09531578
    • 2000-03-20
    • Kenji Noda
    • Kenji Noda
    • H01L2976
    • H01L27/11H01L27/105H01L27/1112H01L27/1116Y10S257/903
    • A plurality of p wells and a plurality of n wells are formed in a p-type semiconductor substrate having a memory portion and a peripheral circuit portion. Next, a resist pattern is formed on the semiconductor substrate. The resist pattern has apertures which, as viewed from the direction normal to the plane of the semiconductor substrate, approximately coincide with the p wells, wherein the area of aperture openings on the top side of the resist pattern is different from the area of aperture openings on the bottom side of the resist pattern. By using the resist pattern as a mask, p-type ions are injected in a shape approximately the same as that of the aperture opening on the top side or bottom side, whichever has the smaller area. Thereafter, by using the same resist pattern as a mask, n-type ions having enough energy to pass through resist of a predetermined thickness are injected into the p-type semiconductor substrate through areas, located adjacent the apertures in the resist pattern, in which the effective thickness of the resist is small, thereby forming deep n wells so as to cover the p well regions.
    • 在具有存储部分和外围电路部分的p型半导体衬底中形成多个p阱和多个n阱。 接下来,在半导体衬底上形成抗蚀剂图案。 抗蚀剂图案具有从垂直于半导体基板的平面的方向观察的孔,其与p孔大致重合,其中抗蚀剂图案的顶侧上的孔径开口面积不同于孔口的面积 在抗蚀剂图案的底侧。 通过使用抗蚀剂图案作为掩模,将p型离子注入与顶侧或底侧上的孔径大致相同的形状,以较小面积为准。 此后,通过使用与掩模相同的抗蚀剂图案,具有足够能量以通过预定厚度的抗蚀剂的n型离子通过位于抗蚀剂图案中的孔附近的区域注入到p型半导体衬底中,其中 抗蚀剂的有效厚度小,从而形成深孔以覆盖p阱区。
    • 84. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US06373119B1
    • 2002-04-16
    • US09030906
    • 1998-02-26
    • Kenji Noda
    • Kenji Noda
    • H01L2900
    • H01L21/76897H01L21/26586H01L21/76229H01L21/823481H01L29/41766
    • A semiconductor device including a trench element separation structure and adapted to a high degree of integration without having crystal defects produced in a semiconductor substrate, and a method of manufacturing the same. The semiconductor device includes a trench element separation region in a prescribed region of the semiconductor substrate, the wall of the semiconductor substrate which forms an inside surface of a trench is covered with a first insulation film, and a second insulation film and a third insulation film are filled inside the trench being stacked in layers in this order. Or, the semiconductor device includes a trench element separation structure in the prescribed region of the semiconductor substrate of one conduction type, the wall of the semiconductor substrate which forms an inside surface of a trench is covered with a first insulation film, and a second insulation film is filled inside the trench which is covered with the first insulation film, and a diffusion layer of a reverse conduction type is formed on the surface of the semiconductor substrate which forms the side surface of the upper region of the trench.
    • 一种半导体器件及其制造方法,该半导体器件包括沟槽元件分离结构,并且适于在半导体衬底中不产生晶体缺陷的高集成度。 半导体器件包括在半导体衬底的规定区域中的沟槽元件分离区域,形成沟槽内表面的半导体衬底的壁被第一绝缘膜覆盖,第二绝缘膜和第三绝缘膜 填充在沟槽内,按层次顺序层叠。 或者,半导体器件在一个导电型的半导体衬底的规定区域中包括沟槽元件分离结构,形成沟槽内表面的半导体衬底的壁被第一绝缘膜覆盖,第二绝缘层 膜被填充在被第一绝缘膜覆盖的沟槽内部,并且在形成沟槽的上部区域的侧表面的半导体衬底的表面上形成反向导电型扩散层。
    • 85. 发明授权
    • Static RAM having word line driving circuitry shared by all the memory cells provided therein
    • 具有由其中提供的所有存储器单元共享的字线驱动电路的静态RAM
    • US06212124B1
    • 2001-04-03
    • US09499953
    • 2000-02-08
    • Kenji Noda
    • Kenji Noda
    • G11C800
    • G11C11/418
    • A static RAM which features an inclusion of a word line driving circuit shared by all the memory cells in the static RAM is disclosed. The static RAM is comprised of a plurality of four-transistor memory cells arranged in an array. Each of the memory cells includes first and second FETs respectively coupled to bit lines and controlled by word line potential. Further, each of the memory cells further comprises third and fourth cross-coupled FETs respectively coupled in series with the first and second FETs and forming a circuit having two stable states. The word line driving circuit reflects a stable state potential change of each of the plurality of memory cells, and controls an output voltage thereof which is applied to the plurality of memory cells in order to maintain the stable state potential in each of the plurality of memory cells.
    • 公开了一种静态RAM,其特征在于包含由静态RAM中的所有存储单元共享的字线驱动电路。 静态RAM由排列成阵列的多个四晶体管存储单元构成。 每个存储单元包括分别耦合到位线并由字线电位控制的第一和第二FET。 此外,每个存储单元还包括分​​别与第一和第二FET串联耦合的第三和第四交叉耦合FET,并形成具有两个稳定状态的电路。 字线驱动电路反映多个存储单元中的每一个的稳定状态电位变化,并且控制施加到多个存储单元的输出电压,以便在多个存储器的每一个中保持稳定状态电位 细胞。