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81. 发明授权

US09069598B2 Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core 有权
标题翻译：提供逻辑分支与反映独家使用处理器核心的硬件线程特定信息
公开(公告)号：US09069598B2
公开(公告)日：2015-06-30
申请号：US13345002
申请日：2012-01-06
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/455 , G06F9/38
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
摘要翻译：用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器信息。如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行物理寄存器包含信息。

82. 发明授权

US08990816B2 Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core 有权
公开(公告)号：US08990816B2
公开(公告)日：2015-03-24
申请号：US13452745
申请日：2012-04-20
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/52 , G06F9/455 , G06F9/38
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

83. 发明授权

US08862859B2 Efficient support of multiple page size segments 有权
标题翻译：高效地支持多个页面大小的段
公开(公告)号：US08862859B2
公开(公告)日：2014-10-14
申请号：US12775652
申请日：2010-05-07
申请人： Miles R. Dooley , Sundeep Chadha , Naresh Nayar , Randal C. Swanberg
发明人： Miles R. Dooley , Sundeep Chadha , Naresh Nayar , Randal C. Swanberg
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652
摘要： An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported page sizes of the MPS segment associated with the virtual address. The possible TLB index values may be a hash generated using the virtual address and one of the supported page sizes. The TLB is searched for actual TLB index values that match the possible TLB index values calculated using the different supported page sizes. TLB entries associated with those actual TLB index values are checked to determine whether any TLB entry is associated with the virtual address. If no match is found, the real address is retrieved from the PT. The actual page size in the PT is used to generate an actual TLB index value for the virtual address and the TLB entry is inserted into the TLB.
摘要翻译：公开了一种用于改进对微处理器中的MPS段的支持的装置，系统和方法。虚拟地址用于为与虚拟地址相关联的MPS段的每个支持的页面大小生成可能的TLB索引值。可能的TLB索引值可以是使用虚拟地址和支持的页面大小之一生成的哈希值。搜索与使用不同的支持的页面大小计算的可能的TLB索引值相匹配的实际TLB索引值的TLB。检查与这些实际TLB索引值相关联的TLB条目以确定是否有任何TLB条目与虚拟地址相关联。如果没有找到匹配，则从PT检索真实地址。 PT中的实际页面大小用于生成虚拟地址的实际TLB索引值，并将TLB条目插入到TLB中。

84. 发明授权

US08832707B2 Tunable error resilience computing 有权
标题翻译：可调整的错误恢复能力计算
公开(公告)号：US08832707B2
公开(公告)日：2014-09-09
申请号：US12642908
申请日：2009-12-21
申请人： Daniel J. Henderson , Prabhakar N. Kudva , Naresh Nayar , Pia Naoko Sanda , David William Siegel , James Van Oosten , James Xenidis
发明人： Daniel J. Henderson , Prabhakar N. Kudva , Naresh Nayar , Pia Naoko Sanda , David William Siegel , James Van Oosten , James Xenidis
IPC分类号： G06F9/46 , G06F15/173 , G06F9/50
CPC分类号： G06F9/5027 , Y02D10/22
摘要： An attribute of a descriptor associated with a task informs a runtime environment of which instructions a processor is to run to schedule a plurality if resources for completion of the task in accordance with a level of quality of service in a service level agreement.
摘要翻译：与任务相关联的描述符的属性通知运行时环境处理器将要运行的指令，以根据服务级别协议中的服务质量级别来调度多个用于完成任务的资源。

85. 发明授权

US08695010B2 Privilege level aware processor hardware resource management facility 有权
标题翻译：特权级别的处理器硬件资源管理工具
公开(公告)号：US08695010B2
公开(公告)日：2014-04-08
申请号：US13251879
申请日：2011-10-03
申请人： Giles R. Frazier , Michael K. Gschwind , Naresh Nayar
发明人： Giles R. Frazier , Michael K. Gschwind , Naresh Nayar
IPC分类号： G06F9/46
CPC分类号： G06F9/45533 , G06F9/45558 , G06F9/462 , G06F9/5077 , G06F2009/45579
摘要： Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.
摘要翻译：多个机器状态寄存器被包括在处理器核心中，以便区分应用程序，监督线程和管理程序之间的硬件设施的使用。当初始化分区时，所有的设备最初被管理程序禁用。当对残疾设施进行访问时，管理程序将收到访问哪个设施的指示，并在管理程序的机器状态寄存器中设置相应的硬件标志。当应用程序尝试访问禁用的设备时，管理操作系统映像的主管接收到哪个设备被访问的指示，并在主管机器状态寄存器中设置相应的硬件标志。多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态，并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。

86. 发明授权

US08645661B2 Paging partition arbitration of paging devices to shared memory partitions 有权
标题翻译：寻呼设备的寻呼分区仲裁到共享内存分区
公开(公告)号：US08645661B2
公开(公告)日：2014-02-04
申请号：US13445416
申请日：2012-04-12
申请人： Richard L. Arndt , Carol B. Hernandez , Kyle A. Lucke , Timothy R. Marchini , Naresh Nayar , James A. Pafumi
发明人： Richard L. Arndt , Carol B. Hernandez , Kyle A. Lucke , Timothy R. Marchini , Naresh Nayar , James A. Pafumi
IPC分类号： G06F12/00
CPC分类号： G06F9/5077 , G06F11/2094
摘要： A computer implemented method to establish at least one paging partition in a data processing system. The virtualization control point (VCP) reserves up to the subset of physical memory for use in the shared memory pool. The VCP configures at least one logical partition as a shared memory partition. The VCP assigns a paging partition to the shared memory pool. The VCP determines whether a user requests a redundant assignment of the paging partition to the shared memory pool. The VCP assigns a redundant paging partition to the shared memory pool, responsive to a determination that the user requests a redundant assignment. The VCP assigns a paging device to the shared memory pool. The hypervisor may transmit at least one paging request to a virtual asynchronous services interface configured to support a paging device stream.
摘要翻译：一种用于在数据处理系统中建立至少一个寻呼分区的计算机实现的方法。虚拟化控制点（VCP）保留到用于共享内存池的物理内存子集。 VCP将至少一个逻辑分区配置为共享内存分区。 VCP将分页分区分配给共享内存池。 VCP确定用户是否请求分页分区的冗余分配给共享内存池。响应于确定用户请求冗余分配，VCP将冗余分页分区分配给共享内存池。 VCP将分页设备分配给共享内存池。管理程序可以向被配置为支持寻呼设备流的虚拟异步服务接口发送至少一个寻呼请求。

87. 发明授权

US08448006B2 Performing virtual and/or physical resource management for power management 失效
标题翻译：执行电源管理的虚拟和/或物理资源管理
公开(公告)号：US08448006B2
公开(公告)日：2013-05-21
申请号：US12907190
申请日：2010-10-19
申请人： Michael S. Floyd , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg , Malcolm S. Ware
发明人： Michael S. Floyd , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg , Malcolm S. Ware
IPC分类号： G06F1/32
CPC分类号： G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3287 , G06F1/329 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： A mechanism is provided for directed resource folding for power management. The mechanism receives a set of static platform characteristics and a set of dynamic platform characteristics for a set of resources associated with the data processing system thereby forming characteristic information. The mechanism determines whether one or more conditions have been met for each resource in the set of resources using the characteristic information. Responsive to the one or more conditions being met, the mechanism performs a resource optimization to determine at least one of a first subset of resources in the set of resources to keep active and a second subset of resources in the set of resources to dynamically fold. Based on the resource optimization, the mechanism performs either a virtual resource optimization to optimally schedule the first subset of resources or a physical resource optimization to dynamically fold the second subset of resources.
摘要翻译：提供了一种用于电源管理的定向资源折叠的机制。该机制接收与数据处理系统相关联的一组资源的一组静态平台特性和一组动态平台特性，从而形成特征信息。该机制使用特征信息确定资源集合中的每个资源是否满足一个或多个条件。响应于满足的一个或多个条件，机制执行资源优化以确定资源集合中的资源的第一子集中的至少一个以保持活动，并且该资源集合中的资源的第二子集动态地折叠。基于资源优化，该机制执行虚拟资源优化以优化调度资源的第一子集或物理资源优化以动态地折叠资源的第二子集。

88. 发明申请

US20120198202A1 Paging Partition Arbitration Of Paging Devices To Shared Memory Partitions 有权
标题翻译：寻呼设备分页仲裁分享内存分区
公开(公告)号：US20120198202A1
公开(公告)日：2012-08-02
申请号：US13445416
申请日：2012-04-12
申请人： Richard L. Arndt , Carol B. Hernandez , Kyle A. Lucke , Timothy R. Marchini , Naresh Nayar , James A. Pafumi
发明人： Richard L. Arndt , Carol B. Hernandez , Kyle A. Lucke , Timothy R. Marchini , Naresh Nayar , James A. Pafumi
IPC分类号： G06F12/02
CPC分类号： G06F9/5077 , G06F11/2094
摘要： A computer implemented method to establish at least one paging partition in a data processing system. The virtualization control point (VCP) reserves up to the subset of physical memory for use in the shared memory pool. The VCP configures at least one logical partition as a shared memory partition. The VCP assigns a paging partition to the shared memory pool. The VCP determines whether a user requests a redundant assignment of the paging partition to the shared memory pool. The VCP assigns a redundant paging partition to the shared memory pool, responsive to a determination that the user requests a redundant assignment. The VCP assigns a paging device to the shared memory pool. The hypervisor may transmit at least one paging request to a virtual asynchronous services interface configured to support a paging device stream.
摘要翻译：一种用于在数据处理系统中建立至少一个寻呼分区的计算机实现的方法。虚拟化控制点（VCP）保留到用于共享内存池的物理内存子集。 VCP将至少一个逻辑分区配置为共享内存分区。 VCP将分页分区分配给共享内存池。 VCP确定用户是否请求分页分区的冗余分配给共享内存池。响应于确定用户请求冗余分配，VCP将冗余分页分区分配给共享内存池。 VCP将分页设备分配给共享内存池。管理程序可以向被配置为支持寻呼设备流的虚拟异步服务接口发送至少一个寻呼请求。

89. 发明申请

US20110296148A1 Transactional Memory System Supporting Unbroken Suspended Execution 有权
标题翻译：支持不间断暂停执行的事务性内存系统
公开(公告)号：US20110296148A1
公开(公告)日：2011-12-01
申请号：US12788351
申请日：2010-05-27
申请人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
发明人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
IPC分类号： G06F9/312
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30189 , G06F9/3834 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F9/467
摘要： Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.
摘要翻译：在具有处理器和事务存储器的数据处理系统中提供用于在数据处理系统中执行事务的机制。这些机制执行包括修改事务存储器的至少一部分的一个或多个指令的事务。响应于由处理器执行的事务挂起指令，事务被暂停。当事务被暂停时，暂停的代码块以非事务方式执行。确定在事务中止时是否发生中断。响应于在事务中止时发生的中断，事务中止操作被延迟，直到事务中止停止为止。

90. 发明申请

US20110283040A1 Multiple Page Size Segment Encoding 有权
标题翻译：多页大小段编码
公开(公告)号：US20110283040A1
公开(公告)日：2011-11-17
申请号：US12779563
申请日：2010-05-13
申请人： Sundeep Chadha , Cathy May , Naresh Nayar , Randal Craig Swanberg
发明人： Sundeep Chadha , Cathy May , Naresh Nayar , Randal Craig Swanberg
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1018 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F2212/652
摘要： An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.
摘要翻译：一种方法识别用于在存储器中包括的存储器地址字段中存储存储器地址的高位数量。该方法计算不用于存储地址的至少一个最低数量的低阶位，其中计算基于所识别的高位位数。该方法从所识别的地址字段的最低位数的最低位数中的一个中检索数据元素，并且还从所识别的地址字段的最低位数中的一个中检索第二数据元素。

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