专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20130013822A1 HOST CONTROLLER 有权
标题翻译：主机控制器
公开(公告)号：US20130013822A1
公开(公告)日：2013-01-10
申请号：US13618464
申请日：2012-09-14
申请人： Peter Feeley , Robert N. Leibowitz , William H. Radke , Neal A. Galbo , Victor Y. Tsai
发明人： Peter Feeley , Robert N. Leibowitz , William H. Radke , Neal A. Galbo , Victor Y. Tsai
IPC分类号： G06F13/28
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0685 , G06F13/28 , G06F13/32 , G06F13/385 , G06F13/4282
摘要： The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.
摘要翻译：本公开包括用于控制存储器设备的方法，设备和系统。用于控制存储器件实施例的一种方法包括将设备类相关信息和命令存储在主机系统存储器和主机控制器存储器中的一个或多个中，在主机控制器中的寄存器中设置指向该命令的指针，通过主机控制器更多的主机系统内存和主机控制器内存与存储设备; 并用存储器件执行命令。

82. 发明申请

US20130013816A1 STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION 有权
公开(公告)号：US20130013816A1
公开(公告)日：2013-01-10
申请号：US13617525
申请日：2012-09-14
申请人： William H. Radke , Victor Y. Tsai , James Cooke , Neal A. Galbo , Peter Feeley
发明人： William H. Radke , Victor Y. Tsai , James Cooke , Neal A. Galbo , Peter Feeley
IPC分类号： G06F3/00
CPC分类号： G06F13/102 , G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1684 , G06F13/4282 , G11C7/1045 , G11C7/22 , G11C7/222 , Y02D10/14 , Y02D10/151
摘要： The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

83. 发明申请

US20120307559A1 DATA MODULATION FOR GROUPS OF MEMORY CELLS 有权
标题翻译：记忆细胞群的数据调制
公开(公告)号：US20120307559A1
公开(公告)日：2012-12-06
申请号：US13152637
申请日：2011-06-03
申请人： Zhenlei Shen , William H. Radke
发明人： Zhenlei Shen , William H. Radke
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5621 , G11C16/0483 , G11C16/34
摘要： Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of M number of programmed states, where M is greater than a minimum number of programmed states needed to store N/G units of data in one memory cell, and where the programmed state of each memory cell of the group is one of the combination of programmed states.
摘要翻译：用于存储器单元组的数据调制的方法，设备和系统。存储器单元组的数据调制可以包括将N个数据单元调制为编程状态的组合。一组G个存储器单元的每个存储器单元可以被编程为M个编程状态中的一个，其中M大于在一个存储器单元中存储N / G个数据单元所需的编程状态的最小数量，以及其中组的每个存储器单元的编程状态是编程状态的组合之一。

84. 发明申请

US20120243362A1 ADVANCED DETECTION OF MEMORY DEVICE REMOVAL, AND METHODS, DEVICES AND CONNECTORS 有权
标题翻译：高级检测存储器件移除，以及方法，器件和连接器
公开(公告)号：US20120243362A1
公开(公告)日：2012-09-27
申请号：US13482743
申请日：2012-05-29
申请人： James Cooke , Peter Feeley , Victor Tsai , William H. Radke , Neal Galbo , Chad Cobbley
发明人： James Cooke , Peter Feeley , Victor Tsai , William H. Radke , Neal Galbo , Chad Cobbley
IPC分类号： G11C5/14
CPC分类号： G06F13/4068
摘要： Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. The removal terminal may have a dimension that is different from a dimension of a power terminal. Alternatively, the connector may be configured to generate a signal that causes a host to terminate programming or erase operations prior to memory card removal, such as by including a switch that is actuated when the memory device moves to a pre-power loss position.
摘要翻译：提供了用于终止操作的存储器件，连接器和方法，包括响应于在从诸如插座的连接器移除存储器设备期间接收信号而终止诸如编程或擦除操作之类的内部操作的存储器件。存储器装置可以被配置为生成去除信号，例如通过包括专用的移除终端。存储卡可以通过在断电之前终止编程或擦除操作来响应信号。拆卸端子可以具有与电源端子的尺寸不同的尺寸。或者，连接器可以被配置为产生使主机在存储卡移除之前停止编程或擦除操作的信号，诸如通过包括当存储器件移动到功率损耗前位置时被致动的开关。

85. 发明授权

US08239725B2 Data storage with an outer block code and a stream-based inner code 有权
标题翻译：具有外部块代码和基于流的内部代码的数据存储
公开(公告)号：US08239725B2
公开(公告)日：2012-08-07
申请号：US13281007
申请日：2011-10-25
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： H03M13/00
CPC分类号： G06F11/1068 , G11C7/1006 , H03M13/2906 , H03M13/2933
摘要： Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based inner code, that is, concatenating the outer block code with an outer code, the error correction can be further enhanced, enhancing the reliability of the device. This can also permit a relatively small-geometry device to be used in a legacy application.
摘要翻译：装置和方法存储用于诸如NAND闪存阵列的存储器阵列的基于流的错误恢复数据。通常，数据按行业规范进行块编码并存储在存储器阵列中。在块代码的限制内，该技术提供错误的校正。通过应用基于流的内部代码，即，将外部块代码与外部代码连接，可以进一步增强错误校正，增强设备的可靠性。这也可以允许在遗留应用中使用相对小的几何设备。

86. 发明授权

US08209447B2 Device to device flow control within a chain of devices 有权
标题翻译：设备链中的设备到设备流控制
公开(公告)号：US08209447B2
公开(公告)日：2012-06-26
申请号：US12550770
申请日：2009-08-31
申请人： Victor Y. Tsai , William H. Radke , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
发明人： Victor Y. Tsai , William H. Radke , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
IPC分类号： G06F15/16 , G06F3/00
CPC分类号： H04L47/215 , H04L47/10 , H04L47/17
摘要： The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device.
摘要翻译：本公开包括用于设备到设备流控制的方法，设备和系统。在一个或多个实施例中，被配置用于设备到设备流控制的系统包括主机和一连串设备，包括一个或多个存储器设备，它们彼此耦合并被配置为通过相同的主机端口与主机设备进行通信。在一个或多个实施例中，链中的至少一个设备被配置为通过在下游数据分组中发送令牌来调节数据流，该令牌允许来自相应的至少一个设备的下游的设备将上游数据分组发送到各自至少一个设备。

87. 发明授权

US08065583B2 Data storage with an outer block code and a stream-based inner code 有权
标题翻译：具有外部块代码和基于流的内部代码的数据存储
公开(公告)号：US08065583B2
公开(公告)日：2011-11-22
申请号：US11774377
申请日：2007-07-06
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： H03M13/00
CPC分类号： G06F11/1068 , G11C7/1006 , H03M13/2906 , H03M13/2933
摘要： Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based inner code, that is, concatenating the outer block code with an outer code, the error correction can be further enhanced, enhancing the reliability of the device. This can also permit a relatively small-geometry device to be used in a legacy application.
摘要翻译：装置和方法存储用于诸如NAND闪存阵列的存储器阵列的基于流的错误恢复数据。通常，数据按行业规范进行块编码并存储在存储器阵列中。在块代码的限制内，该技术提供错误的校正。通过应用基于流的内部代码，即，将外部块代码与外部代码连接，可以进一步增强错误校正，增强设备的可靠性。这也可以允许在遗留应用中使用相对小的几何设备。

88. 发明授权

US08046542B2 Fault-tolerant non-volatile integrated circuit memory 有权
标题翻译：容错非易失性集成电路存储器
公开(公告)号：US08046542B2
公开(公告)日：2011-10-25
申请号：US11944023
申请日：2007-11-21
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G06F12/00
CPC分类号： G06F12/0223 , G06F11/1068 , G06F12/0246 , G06F2212/2022 , G06F2212/7208 , G11C29/765
摘要： Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices.
摘要翻译：公开了诸如将数据存储在具有卷积编码的诸如NAND闪存的多个非易失性集成电路存储器件中的装置和方法。卷积码的相对较高的码率消耗相对较小的额外的存储空间。在一个实施例中，卷积码扩展到多个存储器件的部分上，而不是集中在特定存储器件的页面内。在一个实施例中，使用m / n的码率，并且卷积码被存储在n个存储器装置中。

89. 发明申请

US20110239093A1 FAULT-TOLERANT NON-VOLATILE INTEGRATED CIRCUIT MEMORY 有权
标题翻译：容错非易失性集成电路存储器
公开(公告)号：US20110239093A1
公开(公告)日：2011-09-29
申请号：US13154150
申请日：2011-06-06
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F12/0223 , G06F11/1068 , G06F12/0246 , G06F2212/2022 , G06F2212/7208 , G11C29/765
摘要： Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices.
摘要翻译：公开了诸如将数据存储在具有卷积编码的诸如NAND闪存的多个非易失性集成电路存储器件中的装置和方法。卷积码的相对较高的码率消耗相对较小的额外的存储空间。在一个实施例中，卷积码扩展到多个存储器件的部分上，而不是集中在特定存储器件的页面内。在一个实施例中，使用m / n的码率，并且卷积码被存储在n个存储器装置中。

90. 发明申请

US20110078336A1 STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION 有权
标题翻译：在具有连接配置中的设备的系统中的状态更改
公开(公告)号：US20110078336A1
公开(公告)日：2011-03-31
申请号：US12569661
申请日：2009-09-29
申请人： William H. Radke , Victor Y. Tsai , James Cooke , Neal A. Galbo , Peter Feeley
发明人： William H. Radke , Victor Y. Tsai , James Cooke , Neal A. Galbo , Peter Feeley
IPC分类号： G06F3/00
CPC分类号： G06F13/102 , G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1684 , G06F13/4282 , G11C7/1045 , G11C7/22 , G11C7/222 , Y02D10/14 , Y02D10/151
摘要： The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.
摘要翻译：本公开包括用于在具有以链式配置耦合的设备的系统中的状态改变的方法，设备和系统。许多实施例包括以链式配置耦合到主机的主机和多个设备。链接配置包括至少一个不直接耦合到主机的设备。不直接耦合到主机的至少一个设备被配置为响应于从主机接收到命令而从第一通信状态改变到第二通信状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式