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81. 发明授权

US06869889B1 Etching metal carbide films 失效
标题翻译：蚀刻金属碳化物膜
公开(公告)号：US06869889B1
公开(公告)日：2005-03-22
申请号：US10819789
申请日：2004-04-07
申请人： Justin K. Brask , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Suman Datta , Uday Shah , Terence Bacuita , Robert S. Chau
发明人： Justin K. Brask , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Suman Datta , Uday Shah , Terence Bacuita , Robert S. Chau
IPC分类号： H01L21/302 , H01L21/3213 , H01L21/8234 , H01L29/49
CPC分类号： H01L21/82345 , H01L21/32134 , H01L29/4966
摘要： A metal carbide film may be etched in an etchant bath using sonication. The sonication may drive the reaction and, particularly, the gaseous byproducts in the form of carbon dioxide. Thus, the use of sonication invokes a favorable equilibrium to pattern metal carbide films, for example, for use as metal gate electrodes.
摘要翻译：可以使用超声处理在蚀刻液浴中蚀刻金属碳化物膜。超声处理可以驱动反应，特别是二氧化碳形式的气态副产物。因此，使用超声处理引起对图案金属碳化物膜的有利平衡，例如用作金属栅电极。

82. 发明申请

US20150255711A1 PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH ENHANCED STABILITY AND METHOD TO FORM SAME 审中-公开
标题翻译：具有增强稳定性的全速转子扭矩记忆（STTM）装置及其形成方法
公开(公告)号：US20150255711A1
公开(公告)日：2015-09-10
申请号：US14723310
申请日：2015-05-27
申请人： Brian S. Doyle , Charles C. Kuo , Kaan Oguz , Uday Shah , Elijah V. Karpov , Roksana Golizadeh Mojarad , Mark L. Doczy , Robert S. Chau
发明人： Brian S. Doyle , Charles C. Kuo , Kaan Oguz , Uday Shah , Elijah V. Karpov , Roksana Golizadeh Mojarad , Mark L. Doczy , Robert S. Chau
IPC分类号： H01L43/10 , H01L43/08 , H01L43/12
CPC分类号： H01L43/10 , G11C11/161 , G11C11/18 , H01F10/14 , H01F10/16 , H01F10/1936 , H01F10/3236 , H01F10/3286 , H01F10/329 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12
摘要： Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.
摘要翻译：描述了具有增强的稳定性的垂直自旋转移转矩存储器（STTM）装置和制造具有增强的稳定性的垂直STTM装置的方法。例如，用于磁隧道结的材料层堆叠包括固定磁性层。电介质层设置在固定磁性层的上方。自由磁性层设置在电介质层的上方。导电氧化物材料层设置在自由磁性层上。

83. 发明申请

US20150102429A1 SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES 审中-公开
公开(公告)号：US20150102429A1
公开(公告)日：2015-04-16
申请号：US14576111
申请日：2014-12-18
申请人： Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Uday Shah , Suman Datta , Amlan Majumdar , Robert S. Chau
发明人： Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Uday Shah , Suman Datta , Amlan Majumdar , Robert S. Chau
IPC分类号： H01L29/04 , H01L21/308 , H01L29/78
CPC分类号： H01L29/7853 , H01L21/30608 , H01L21/30617 , H01L21/3085 , H01L21/84 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/51 , H01L29/66795 , H01L29/78681 , H01L29/78684
摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

84. 发明申请

US20140329337A1 PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME 有权
标题翻译：具有偏心电极的PERPENDICULAR SPIN TRANSFER TORQUE MEMORY（STTM）装置及其形成方法
公开(公告)号：US20140329337A1
公开(公告)日：2014-11-06
申请号：US14333180
申请日：2014-07-16
申请人： Brian S. Doyle , David L. Kencke , Charles C. Kuo , Uday Shah , Kaan Oguz , Mark L. Doczy , Satyarth Suri , Clair Webb
发明人： Brian S. Doyle , David L. Kencke , Charles C. Kuo , Uday Shah , Kaan Oguz , Mark L. Doczy , Satyarth Suri , Clair Webb
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1659 , H01L27/222 , H01L27/228 , H01L29/66007 , H01L29/82 , H01L43/02 , H01L43/08 , H01L43/10
摘要： Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
摘要翻译：描述具有偏移单元的垂直自旋转移转矩存储器（STTM）器件和制造具有偏置单元的垂直STTM器件的方法。例如，自旋转矩传递存储器（STTM）阵列包括设置在衬底上方并且仅具有第一STTM器件的第一负载线。 STTM阵列还包括设置在基板上方的第二负载线，与第一负载线相邻，并且仅具有第二STTM器件，与第一STTM器件非共面的第二STTM器件。

85. 发明授权

US08581258B2 Semiconductor device structures and methods of forming semiconductor structures 失效
公开(公告)号：US08581258B2
公开(公告)日：2013-11-12
申请号：US13277897
申请日：2011-10-20
申请人： Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Uday Shah , Suman Datta , Amlan Majumdar , Robert S. Chau
发明人： Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Uday Shah , Suman Datta , Amlan Majumdar , Robert S. Chau
IPC分类号： H01L21/00
CPC分类号： H01L29/7853 , H01L21/30608 , H01L21/30617 , H01L21/3085 , H01L21/84 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/51 , H01L29/66795 , H01L29/78681 , H01L29/78684
摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

86. 发明申请

US20120326274A1 SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED QUADRUPLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME 有权
标题翻译：具有用于嵌入式动态随机存取存储器（EDRAM）的集成四元组电容器的半导体结构及其形成方法
公开(公告)号：US20120326274A1
公开(公告)日：2012-12-27
申请号：US13165615
申请日：2011-06-21
申请人： Brian S. Doyle , Uday Shah , Satyarth Suri , Ramanan V. Chebiam
发明人： Brian S. Doyle , Uday Shah , Satyarth Suri , Ramanan V. Chebiam
IPC分类号： H01L29/92 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L27/10894 , H01L28/91
摘要： Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.
摘要翻译：描述了具有用于eDRAM的集成四足壁电容器的半导体结构及其形成方法。例如，嵌入式四壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。沟槽有一个底部和侧壁。金属板的四重布置设置在沟槽的底部，与侧壁间隔开。第二电介质层设置在沟槽的侧壁和金属板的四重布置上。顶部金属板层设置在第二介电层上并与第二介质层保形。

87. 发明授权

US08119508B2 Forming integrated circuits with replacement metal gate electrodes 有权
标题翻译：用替换金属栅电极形成集成电路
公开(公告)号：US08119508B2
公开(公告)日：2012-02-21
申请号：US12781084
申请日：2010-05-17
申请人： Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew V. Metz , Suman Datta , Uday Shah , Robert S. Chau
发明人： Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew V. Metz , Suman Datta , Uday Shah , Robert S. Chau
IPC分类号： H01L21/20
CPC分类号： H01L27/092 , H01L21/28114 , H01L21/823842 , H01L21/82385 , H01L29/66545
摘要： In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
摘要翻译：在金属栅极更换工艺中，可以形成至少两个多晶硅层或其它材料的堆叠。侧壁间隔物可以形成在堆叠上。然后可以将堆叠平坦化。接下来，可以选择性地去除堆叠的上层。然后，可以选择性地去除侧壁间隔物的暴露部分。最后，堆叠的下部可以被去除以形成可以用金属替代物填充的T形沟槽。

88. 发明申请

US20110156004A1 Multi-gate III-V quantum well structures 有权
标题翻译：多栅III-V量子阱结构
公开(公告)号：US20110156004A1
公开(公告)日：2011-06-30
申请号：US12655463
申请日：2009-12-30
申请人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
发明人： Marko Radosavljevic , Uday Shah , Gilbert Dewey , Niloy Mukherjee , Robert S. Chau , Jack Kavalieros , Ravi Pillarisetty , Titash Rakshit , Matthew V. Metz
IPC分类号： H01L29/775 , H01L21/20 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42364 , H01L29/66462 , H01L29/66795 , H01L29/7786 , H01L29/785
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括在基板上形成III-V三栅极翅片，在III-V三栅极鳍周围形成包层材料，以及在包层材料周围形成Hi栅极电介质。

89. 发明申请

US20110147812A1 POLISH TO REMOVE TOPOGRAPHY IN SACRIFICIAL GATE LAYER PRIOR TO GATE PATTERNING 有权
标题翻译：在移动栅栏之前，移除邻近门控层的波形
公开(公告)号：US20110147812A1
公开(公告)日：2011-06-23
申请号：US12646450
申请日：2009-12-23
申请人： Joseph M. Steigerwald , Uday Shah , Seiichi Morimoto , Nancy Zelick
发明人： Joseph M. Steigerwald , Uday Shah , Seiichi Morimoto , Nancy Zelick
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/28123 , H01L29/66545 , H01L29/785
摘要： Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e.g., flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e.g., flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin.
摘要翻译：公开了用于制造FinFET晶体管（例如，双栅极，三极管等）的技术。牺牲栅极材料（例如多晶硅或其他合适的材料）沉积在鳍结构上，并且在栅极图案化之前抛光以去除牺牲栅极材料层中的形貌。平坦的，无地形的表面（例如，取决于形成的最小特征的尺寸，平均度为50nm或更好）使得后续的栅极图案化和牺牲栅极材料在FinFET工艺流程中打开（经由抛光）。使用本文描述的技术可以以结构方式表现。例如，当栅极在翅片上行进时，顶栅表面相对平坦（例如，平均度为5至50nm，取决于最小栅极高度或其他最小特征尺寸）。此外，栅极线的自顶向下检查通常将显示没有或最小的线边缘偏离或扰动，因为线在翅片上延伸。

90. 发明申请

US20110147711A1 NON-PLANAR GERMANIUM QUANTUM WELL DEVICES 有权
标题翻译：非平面德国量子井设备
公开(公告)号：US20110147711A1
公开(公告)日：2011-06-23
申请号：US12646477
申请日：2009-12-23
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L29/06 , H01L21/338
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译：公开了用于形成非平面锗量子阱结构的技术。特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。栅极金属可以跨鳍片结构沉积。排水/源极区域可以形成在翅片结构的相应端部处。

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