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81. 发明申请

US20080238477A1 TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE 审中-公开
标题翻译：可行的可编程门阵列架构
公开(公告)号：US20080238477A1
公开(公告)日：2008-10-02
申请号：US12036470
申请日：2008-02-25
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.
摘要翻译：一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

82. 发明授权

US07426665B1 Tileable field-programmable gate array architecture 有权
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US07426665B1
公开(公告)日：2008-09-16
申请号：US10066539
申请日：2002-01-30
申请人： Jung-Cheun Lien , Chung-Yuan Sun , Tong Liu , Zili Zhang , Sheng Feng , Eddy C. Huang , Naihui Liao
发明人： Jung-Cheun Lien , Chung-Yuan Sun , Tong Liu , Zili Zhang , Sheng Feng , Eddy C. Huang , Naihui Liao
IPC分类号： G01R31/28 , G06F17/50 , G06F7/38
CPC分类号： H03K19/17764 , H03K17/693 , H03K19/17736
摘要： A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks, defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks, determining an expected logic result for a selected logical combination of the individual test inputs, applying the individual test inputs to the first end of each of the at least two of the first sets of tracks, performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result, and flagging an error if the actual result is not identical with the expected logic result.
摘要翻译：一种用于测试具有可编程可连接的各个轨道段的多个第一组轨道的FPGA路由电路的方法，包括提供全局控制信号，以同时打开所述第一组轨道中的至少两个中的所有可编程元件，输入以应用于所述至少两个第一组轨道中的每一个的第一端，确定所选择的各个测试输入的逻辑组合的预期逻辑结果，将各个测试输入应用于每个所述第一组轨道中的至少两个，在所述第一组轨道的所述至少两个轨道的所述第二端上执行所选择的逻辑组合，以产生实际的逻辑结果，以及如果所述实际结果与预期的逻辑结果。

83. 发明申请

US20080043352A1 Lightweight mirrors and methods of manufacturing lightweight mirrors 审中-公开
标题翻译：轻型镜子和制造轻型镜子的方法
公开(公告)号：US20080043352A1
公开(公告)日：2008-02-21
申请号：US11788463
申请日：2007-04-20
申请人： Tong Liu
发明人： Tong Liu
IPC分类号： G02B7/192
CPC分类号： G02B7/183
摘要： A lightweight mirror comprises a plurality of plates including an optical plate, a backing plate, spacer plates, and, if needed, one or more reinforcing plates. The plates are joined to one another thereby forming a unitary structure. The unitary structure comprising the plates is then formed into a predetermined optical mirror configuration.
摘要翻译：轻质镜子包括多个板，包括光学板，背板，间隔板，以及如果需要的话，一个或多个加强板。板彼此接合，从而形成一体的结构。然后将包括板的单一结构形成为预定的光学镜构造。

84. 发明申请

US20070089082A1 FREEWAY ROUTING SYSTEM FOR A GATE ARRAY 审中-公开
标题翻译：一个门阵列的自由路由系统
公开(公告)号：US20070089082A1
公开(公告)日：2007-04-19
申请号：US11557717
申请日：2006-11-08
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.
摘要翻译：高速公路路由系统，用于连接现场可编程门阵列中瓦片接口组的输入和输出端口。高速公路系统具有第一组路由导体，其被配置为在现场可编程门阵列的第一瓦片中的接口组的输入端口与现场可编程门阵列中的其它瓦片的接口组的输出端口之间传送信号。第一组导体包括垂直导体，其形成与水平导体和位于垂直导体和水平导体的交叉点处的对准取向的可编程互连元件的交点，以将每个水平导体连接到一个垂直导体。

85. 发明申请

US20060198386A1 System and method for distributed information handling system cluster active-active master node 审中-公开
标题翻译：分布式信息处理系统集群主动主节点的系统与方法
公开(公告)号：US20060198386A1
公开(公告)日：2006-09-07
申请号：US11069770
申请日：2005-03-01
申请人： Tong Liu , Onur Celebioglu , Yung-Chin Fang
发明人： Tong Liu , Onur Celebioglu , Yung-Chin Fang
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L67/32 , H04L69/40
摘要： Computing nodes, such as plural information handling systems configured as a High Performance Computing Cluster (HPCC), are managed with plural master nodes configured to have active-active interaction. A resource manager of each of the plural master nodes is operable to simultaneously assign computing node resources to job requests. Reservations are made by a job scheduler in a table of a storage common to the active-active master nodes to avoid conflicts between master nodes and then reserved computing resources are assigned for management by the reserving master node resource manager. A failure manager monitors the master nodes to detect a failure, such as by a lack of communication from a master node for a predetermined time, and recovers a failed master node by assigning the jobs associated with the failed master node to an operating master node.
摘要翻译：诸如配置为高性能计算群集（HPCC）的多个信息处理系统的计算节点由配置成具有主动 - 主动交互的多个主节点来管理。多个主节点中的每一个的资源管理器可操作以将计算节点资源同时分配给作业请求。由主动主节点共用的存储的表中的作业调度器进行预约，以避免主节点之间的冲突，然后由保留的主节点资源管理器分配保留的计算资源以进行管理。故障管理器监视主节点以检测故障，例如在预定时间内缺少主节点的通信，并通过将与故障主节点相关联的作业分配给操作主节点来恢复故障主节点。

86. 发明授权

US07053653B1 Inter-tile buffer system for a field programmable gate array 失效
标题翻译：用于现场可编程门阵列的片间缓冲系统
公开(公告)号：US07053653B1
公开(公告)日：2006-05-30
申请号：US10916811
申请日：2004-08-11
申请人： Sheng Feng , Tong Liu , Jung-Cheun Lien
发明人： Sheng Feng , Tong Liu , Jung-Cheun Lien
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H01L27/118
摘要： An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each tile comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA tile, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.
摘要翻译：一种用于现场可编程门阵列（FPGA）的片间缓冲系统，包括以行和列排列的多个FPGA片。每个瓦片包括多个功能和接口组以及主要路由结构，该主要路由结构耦合到功能和接口组，并且被配置为在至少一个FPGA瓦片内接收和路由主输出信号，并且向主要输入信号提供功能和接口组。每个功能组被配置为接收输入信号，执行逻辑操作并产生输出信号，并且被配置为将信号从路由结构传送到至少一个FPGA平铺的外部，并且包括多个输入多路复用器，被配置为选择从外部至少一个FPGA瓦片，并向至少一个FPGA瓦片内的路由结构提供信号。

87. 发明授权

US07015719B1 Tileable field-programmable gate array architecture 有权
公开(公告)号：US07015719B1
公开(公告)日：2006-03-21
申请号：US11056957
申请日：2005-02-11
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

88. 发明申请

US20050255164A1 Solid nano pharmaceutical formulation and preparation method thereof 审中-公开
标题翻译：固体纳米药物制剂及其制备方法
公开(公告)号：US20050255164A1
公开(公告)日：2005-11-17
申请号：US10524808
申请日：2003-08-13
申请人： Yunging Liu , Xiying Liu , Wei Liu , Tong Liu
发明人： Yunging Liu , Xiying Liu , Wei Liu , Tong Liu
IPC分类号： A61K9/10 , A61K9/127 , A61K9/14 , A61K31/337 , A61K31/724 , A61K47/24 , A61K47/40
CPC分类号： A61K31/337 , A61K9/0019 , A61K9/1075 , A61K9/5123 , A61K9/5138 , A61K9/5161 , A61K47/6951 , B82Y5/00
摘要： A method of preparing low water-soluble medicine into solid nanometer pharmaceutical formulation is disclosed. According to the characters of molecular aggregates such as supramolecular chemical micelles and vesicles, the formulation, which based on the hydroxypropyl-beta-cyclodextrin and phospholipid, is prepared under the condition of hyperthermia sterilization and decompression. Such nanometer formulation is sterile particle or powder with loose porosity. For directly intravenous use, the formulation has targeting activity, sustained release and long circulating characters. While as a solid oral product, it is fast-release, fast-effective, and improved bioavailability characters, and is readily melted in mouth. The formulation utilizes secure accessories, traditional equipments and methods, thus, it is suited to be used and manufactured widely. Also disclosed is intravenous formulation of anticancer paclitaxel, which characterized that there has no polyoxyethylenated castor oil in it. Such intravenous formulation is nonallergic so that it has higher security and efficiency compared to present commercially available paclitaxel formulations.
摘要翻译：公开了一种将低水溶性药物制备成固体纳米药物制剂的方法。根据超分子化学胶束和囊泡等分子聚集体的特点，在高温灭菌和减压条件下制备基于羟丙基-β-环糊精和磷脂的制剂。这种纳米制剂是具有松散孔隙率的无菌颗粒或粉末。为了直接静脉使用，该制剂具有靶向活性，持续释放和长循环特征。作为固体口服产品，它是快速释放，快速有效的和改善的生物利用度特征，并且容易在口中熔化。该配方采用安全附件，传统设备和方法，因此适用于广泛使用和制造。还公开了抗癌紫杉醇的静脉内制剂，其特征在于其中没有聚氧乙烯化的蓖麻油。这种静脉内制剂是非过敏性的，因此与现有的市售紫杉醇制剂相比，其具有更高的安全性和效率。

89. 发明授权

US06476636B1 Tileable field-programmable gate array architecture 失效
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US06476636B1
公开(公告)日：2002-11-05
申请号：US09654240
申请日：2000-09-02
申请人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
发明人： Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.
摘要翻译：一种装置包括现场可编程门阵列（FPGA）。 FPGA包括第一FPGA片，并且第一FPGA片包括多个功能组（FG），规则路由结构以及多个接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收常规输入信号，执行逻辑运算并产生规则的输出信号。常规路由结构耦合到FG并被配置成接收常规输出信号，在第一FPGA片内路由信号，并向FG提供常规输入信号。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到常规路由结构并且被配置为将信号从常规路由结构传送到第一FPGA块的外部。

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