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    • 81. 发明授权
    • Calculation processing apparatus and control method thereof
    • 计算处理装置及其控制方法
    • US08385631B2
    • 2013-02-26
    • US13155640
    • 2011-06-08
    • Takahisa YamamotoMasami KatoYoshinori Ito
    • Takahisa YamamotoMasami KatoYoshinori Ito
    • G06K9/62
    • G06N3/08
    • A calculation processing apparatus, which executes calculation processing based on a network composed by hierarchically connecting a plurality of processing nodes, assigns a partial area of a memory to each of the plurality of processing nodes, stores a calculation result of a processing node in a storable area of the partial area assigned to that processing node, and sets, as storable areas, areas that store the calculation results whose reference by all processing nodes connected to the subsequent stage of that processing node is complete. The apparatus determines, based on the storage states of calculation results in partial areas of the memory assigned to the processing node designated to execute the calculation processing of the processing nodes, and to processing nodes connected to the previous stage of the designated processing node, whether or not to execute a calculation of the designated processing node.
    • 执行基于通过分层连接多个处理节点组成的网络的计算处理的计算处理装置,将多个处理节点中的每个处理节点的存储器的部分区域分配,将处理节点的计算结果存储在可存储 分配给该处理节点的部分区域的区域,并且存储存储连接到该处理节点的后续阶段的所有处理节点的参考的计算结果的存储区域。 该装置基于分配给指定用于执行处理节点的计算处理的处理节点的存储器的部分区域中的计算结果的存储状态以及连接到指定处理节点的前一级的处理节点,确定是否 或者不执行指定的处理节点的计算。
    • 84. 发明申请
    • CALCULATION PROCESSING APPARATUS AND CONTROL METHOD THEREOF
    • 计算处理装置及其控制方法
    • US20110239224A1
    • 2011-09-29
    • US13155640
    • 2011-06-08
    • Takahisa YamamotoMasami KatoYoshinori Ito
    • Takahisa YamamotoMasami KatoYoshinori Ito
    • G06F9/46
    • G06N3/08
    • A calculation processing apparatus, which executes calculation processing based on a network composed by hierarchically connecting a plurality of processing nodes, assigns a partial area of a memory to each of the plurality of processing nodes, stores a calculation result of a processing node in a storable area of the partial area assigned to that processing node, and sets, as storable areas, areas that store the calculation results whose reference by all processing nodes connected to the subsequent stage of that processing node is complete. The apparatus determines, based on the storage states of calculation results in partial areas of the memory assigned to the processing node designated to execute the calculation processing of the processing nodes, and to processing nodes connected to the previous stage of the designated processing node, whether or not to execute a calculation of the designated processing node.
    • 执行基于通过分层连接多个处理节点组成的网络的计算处理的计算处理装置,将多个处理节点中的每个处理节点的存储器的部分区域分配,将处理节点的计算结果存储在可存储 分配给该处理节点的部分区域的区域,并且存储存储连接到该处理节点的后续阶段的所有处理节点的参考的计算结果的存储区域。 该装置基于分配给指定用于执行处理节点的计算处理的处理节点的存储器的部分区域中的计算结果的存储状态以及连接到指定处理节点的前一级的处理节点,确定是否 或者不执行指定的处理节点的计算。
    • 85. 发明申请
    • CONVOLUTION OPERATION CIRCUIT AND OBJECT RECOGNITION APPARATUS
    • 调查操作电路和对象识别装置
    • US20110239032A1
    • 2011-09-29
    • US13132316
    • 2009-12-03
    • Masami KatoTakahisa YamamotoYoshinori Ito
    • Masami KatoTakahisa YamamotoYoshinori Ito
    • G06F1/14
    • G06N3/06G06F17/15G06K9/00281G06K9/6217G06N3/063G06N5/02G06T1/00
    • In a convolution operation circuit, a first and a second shift registers provide data to a first and a second inputs of a plurality of multipliers, a first and a second storage units store data to be supplied to the first and the second shift registers, a plurality of cumulative adders accumulate output from the plurality of multipliers, a third storage unit latches output from the plurality of cumulative adders at predetermined timing, a fourth storage unit stores data to be stored in the first and the second storage units and data output from the third storage unit, and a control unit sets data stored in the first and the second storage units to the first and the second shift registers at predetermined timing, causes the first and the second shift registers to perform shift operations in synchronization with an operation of the cumulative adder.
    • 在卷积运算电路中,第一和第二移位寄存器向多个乘法器的第一和第二输入提供数据,第一和第二存储单元存储要提供给第一和第二移位寄存器的数据, 多个累积加法器累积来自多个乘法器的输出,第三存储单元以预定定时锁存多个累积加法器的输出,第四存储单元存储要存储在第一和第二存储单元中的数据以及从 第三存储单元和控制单元以预定定时将存储在第一和第二存储单元中的数据设置到第一和第二移位寄存器,使得第一和第二移位寄存器与第一和第二移位寄存器的操作同步地执行移位操作 累加器。