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81. 发明授权

US08841188B2 Bulk finFET with controlled fin height and high-K liner 有权
标题翻译：散装finFET具有可控翅片高度和高K衬垫
公开(公告)号：US08841188B2
公开(公告)日：2014-09-23
申请号：US13604658
申请日：2012-09-06
申请人： Alexander Reznicek , Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz
发明人： Alexander Reznicek , Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924 , H01L29/0684 , H01L29/1054 , H01L29/66795
摘要： A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底上形成材料堆叠，所述材料堆叠包括在所述衬底上的第一介电层，所述第一电介质层上的第二电介质层和所述第二电介质层上的第三电介质层，其中所述第二电介质层是高k电介质。通过材料堆叠形成开口以暴露半导体衬底的表面。通过材料堆叠在开口中形成半导体材料。第一电介质层被选择性地去除到第二电介质层和半导体材料。栅极结构形成在半导体材料的沟道部分上。在一些实施例中，该方法可以提供多个finFET或者触发半导体器件，其中这些器件的鳍结构具有基本上相同的高度。

82. 发明授权

US08841185B2 High density bulk fin capacitor 有权
标题翻译：高密度散装散热片电容器
公开(公告)号：US08841185B2
公开(公告)日：2014-09-23
申请号：US13584176
申请日：2012-08-13
申请人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L28/92 , H01L27/0805 , H01L29/785
摘要： A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors.
摘要翻译：公开了一种高密度散装散热片电容器。通过进一步蚀刻散热片电容器以提供更多的表面积，从而在finFET附近形成翅片电容器，从而增加电容密度。本发明的实施例包括耗尽型变容二极管和反模式变容二极管。

83. 发明授权

US08648388B2 High performance multi-finger strained silicon germanium channel PFET and method of fabrication 失效
标题翻译：高性能多指应变硅锗通道PFET及其制造方法
公开(公告)号：US08648388B2
公开(公告)日：2014-02-11
申请号：US13396970
申请日：2012-02-15
申请人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/0642 , H01L29/0692 , H01L29/41783 , H01L29/4236 , H01L29/66575 , H01L29/66628
摘要： A field effect transistor and method of fabrication are provided. The field effect transistor comprises a plurality of elongated uniaxially-strained SiGe regions disposed on a silicon substrate, oriented such that they are in parallel to the direction of flow of electrical carriers in the channel. The elongated uniaxially-strained SiGe regions are oriented perpendicular to, and traverse through the transistor gate.
摘要翻译：提供场效应晶体管及其制造方法。场效应晶体管包括设置在硅衬底上的多个细长的单轴应变SiGe区域，其定向成使得它们与通道中的电载体的流动方向平行。细长的单轴应变SiGe区域垂直于晶体管栅极定向并穿过晶体管栅极。

84. 发明申请

US20130270655A1 SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES 有权
标题翻译：具有精细结构的半导体器件，以及形成具有结构的半导体器件的方法
公开(公告)号：US20130270655A1
公开(公告)日：2013-10-17
申请号：US13448749
申请日：2012-04-17
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/336 , H01L21/20
CPC分类号： H01L29/78 , H01L21/02532 , H01L21/0262 , H01L21/20 , H01L29/66477 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.
摘要翻译：一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。外延半导体材料与至少两个翅片结构直接接触。

85. 发明申请

US20130270638A1 STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX 审中-公开
标题翻译：外延生长框架上的应变SOI结构
公开(公告)号：US20130270638A1
公开(公告)日：2013-10-17
申请号：US13445959
申请日：2012-04-13
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/165 , H01L29/66795 , H01L29/7848
摘要： A semiconductor structure includes an epitaxial insulator layer located on a substrate. A fin structure is located on the epitaxial insulator layer, where at least one epitaxial source-drain region having an embedded stressor is located on the epitaxial insulator layer and abuts at least one sidewall associated with the fin structure. The epitaxial source-drain region having the embedded stressor provides stress along the fin structure such that the provided stress is based on a lattice mismatch between the epitaxial source-drain region, and both the epitaxial insulator layer and the one side-wall associated with the fin structure.
摘要翻译：半导体结构包括位于衬底上的外延绝缘体层。翅片结构位于外延绝缘体层上，其中具有嵌入的应力源的至少一个外延源极 - 漏极区域位于外延绝缘体层上并邻接与翅片结构相关联的至少一个侧壁。具有嵌入的应力源的外延源极 - 漏极区域沿着鳍状结构提供应力，使得所提供的应力基于外延源极 - 漏极区域和外延绝缘体层与与该外部源极 - 漏极区域相关联的一个侧壁之间的晶格失配翅片结构。

86. 发明申请

US20130270611A1 SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS 有权
标题翻译：具有反射面的源和漏极的半导体结构
公开(公告)号：US20130270611A1
公开(公告)日：2013-10-17
申请号：US13446350
申请日：2012-04-13
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/02579 , H01L21/02609 , H01L21/84 , H01L29/0657 , H01L29/0847 , H01L29/78
摘要： A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.
摘要翻译：包括半导体晶片的半导体结构。所述半导体晶片包括栅极结构，所述半导体晶片中与所述栅极结构的第一侧相邻的第一沟槽和与所述栅极结构的第二侧相邻的第二沟槽，所述第一和第二沟槽填充有掺杂的外延硅，在填充的第一沟槽中形成源极，并且在填充的第二沟槽中形成漏极，使得源极和漏极中的每一个凹入并具有倒置的面。在优选的示例性实施例中，外延硅掺杂有硼。

87. 发明申请

US20130207162A1 HIGH PERFORMANCE MULTI-FINGER STRAINED SILICON GERMANIUM CHANNEL PFET AND METHOD OF FABRICATION 失效
标题翻译：高性能多指纹应变硅锗通道PFET及其制造方法
公开(公告)号：US20130207162A1
公开(公告)日：2013-08-15
申请号：US13396970
申请日：2012-02-15
申请人： ALI KHAKIFIROOZ , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
发明人： ALI KHAKIFIROOZ , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/336 , B82Y99/00
CPC分类号： H01L29/1054 , H01L29/0642 , H01L29/0692 , H01L29/41783 , H01L29/4236 , H01L29/66575 , H01L29/66628
摘要： A field effect transistor and method of fabrication are provided. The field effect transistor comprises a plurality of elongated uniaxially-strained SiGe regions disposed on a silicon substrate, oriented such that they are in parallel to the direction of flow of electrical carriers in the channel. The elongated uniaxially-strained SiGe regions are oriented perpendicular to, and traverse through the transistor gate.
摘要翻译：提供场效应晶体管及其制造方法。场效应晶体管包括设置在硅衬底上的多个细长的单轴应变SiGe区域，其定向成使得它们与通道中的电载体的流动方向平行。细长的单轴应变SiGe区域垂直于晶体管栅极定向并穿过晶体管栅极。

88. 发明申请

US20130146952A1 ON-CHIP CAPACITORS IN COMBINATION WITH CMOS DEVICES ON EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) SUBSTRATES 有权
公开(公告)号：US20130146952A1
公开(公告)日：2013-06-13
申请号：US13314238
申请日：2011-12-08
申请人： THOMAS N. ADAM , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： THOMAS N. ADAM , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/088 , H01L21/336 , H01L21/02
CPC分类号： H01L27/1203 , H01L27/0629 , H01L29/94
摘要： A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material.

89. 发明授权

US09093260B2 Thin hetereostructure channel device 有权
标题翻译：薄型立体声通道装置
公开(公告)号：US09093260B2
公开(公告)日：2015-07-28
申请号：US13607875
申请日：2012-09-10
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/66 , H01L21/02 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L21/3065 , H01L29/10
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

90. 发明授权

US09087687B2 Thin heterostructure channel device 有权
标题翻译：薄异质结构通道器件
公开(公告)号：US09087687B2
公开(公告)日：2015-07-21
申请号：US13336251
申请日：2011-12-23
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/84 , H01L27/12 , H01L21/3065 , H01L29/10
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

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