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81. 发明申请

US20120236628A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US20120236628A1
公开(公告)日：2012-09-20
申请号：US13511787
申请日：2011-11-24
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array plane in a Y direction are adjacent to each other in the Y direction, and the first via group in the second basic array plane is connected to an unselected-bit-line dedicated global bit line (GBL_NS) having a fixed potential when the first via group in the first basic array plane is connected to a first global bit line related to the first basic array plane.
摘要翻译：在非易失性存储器件中，基本阵列平面（0至3）具有各自的第一通孔组（121至124），其仅互连基本阵列平面中的偶数位线，以及相互连接的相应的第二通孔组（131至134）在基本阵列平面中只有奇数位线，在第一基本阵列平面中的第一通孔组和与Y方向上与第一基本阵列平面相邻的第二基本阵列平面中的第二通孔组彼此相邻， Y方向和第二基本阵列平面中的第一通孔组连接到具有固定电位的未选择位线专用全局位线（GBL_NS），当第一基本阵列平面中的第一通孔组连接到与第一个基本阵列平面相关的第一个全局位线。

82. 发明授权

US08233311B2 Variable resistance nonvolatile storage device having a source line formed of parallel wiring layers connected to each other through vias 有权
标题翻译：可变电阻非易失性存储装置具有通过通孔彼此连接的平行布线形成的源极线
公开(公告)号：US08233311B2
公开(公告)日：2012-07-31
申请号：US13310894
申请日：2011-12-05
申请人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
发明人： Kazuhiko Shimakawa , Yoshihiko Kanzawa , Satoru Mitani , Shunsaku Muraoka
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/32 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt
摘要翻译：可变电阻非易失性存储装置包括通过串联连接可变电阻元件（309）形成的存储单元（300），该可变电阻元件（309）包括基于各自具有不同极性的电信号可逆地改变的可变电阻层（309b）和晶体管（307），包括半导体衬底（301）和两个N型扩散层区域（302a，302b），其中可变电阻层（309b）包括过渡金属的氧缺乏氧化物，下电极和上电极（309a， 309c）的材料由下部电极（309a）的标准电极电位V1，上部电极（309c）的标准电极电位V2，过渡金属的标准电极电位Vt满足Vt

83. 发明申请

US20120176834A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件
公开(公告)号：US20120176834A1
公开(公告)日：2012-07-12
申请号：US13496895
申请日：2011-08-10
申请人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
发明人： Yuichiro Ikeda , Kazuhiko Shimakawa , Ryotaro Azuma
IPC分类号： G11C11/21
CPC分类号： H01L27/101 , G11C13/004 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.
摘要翻译：每个基本阵列平面具有仅在基本阵列平面中互连偶数位线的第一通孔组和仅在基本阵列平面中互连奇数位线的第二通孔组，第一通孔组在第一通孔组在Y方向上与第一基本阵列相邻的第二基本阵列平面中的基本阵列平面和第二通孔组在Y方向上彼此相邻，并且第一基本阵列平面中的第二通孔组和第一通孔组在第二基本阵列平面中在Y方向上彼此相邻，并且当将第一基本阵列平面中的第一通孔组连接到第一全局线阵列时，第二基本阵列平面中的第二通孔组与第二全局线断开连接线。

84. 发明申请

US20120099367A1 CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：交叉点可变电阻非易失性存储器件
公开(公告)号：US20120099367A1
公开(公告)日：2012-04-26
申请号：US13380624
申请日：2011-06-02
申请人： Ryotaro Azuma , Kazuhiko Shimakawa
发明人： Ryotaro Azuma , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , G11C2213/76 , H01L27/0688 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell (51) is placed at a different one of cross points of bit lines (53) in an X direction and word lines (52) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements (57, 58) switch electrical connection and disconnection between a global bit line (56) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit (92) having parallel-connected P-type current limiting element (91) and N-type current limiting element (90) is provided between the global bit line and the switch elements.
摘要翻译：交叉点可变电阻非易失性存储器件包括具有相同取向的存储单元，用于所有层的稳定特性。每个存储单元（51）被放置在X方向上的位线（53）的交叉点的不同的一个和Y层方向上形成的字线（52）。在多路交叉点结构中，共享字线的垂直阵列平面在Y方向上对齐，对于在Z方向上排列的一组位线，偶数和奇数位位线选择开关元件（57,58）切换电连接以及全局位线（56）和共同连接的偶数层位线和共同连接的奇数位位线之间的断开。在全局位线和开关元件之间提供具有并联P型限流元件（91）和N型限流元件（90）的双向限流电路（92）。

85. 发明授权

US08148711B2 Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using nonvolatile memory element 有权
标题翻译：非易失性存储元件及其制造方法以及使用非易失性存储元件的非易失性半导体装置
公开(公告)号：US08148711B2
公开(公告)日：2012-04-03
申请号：US12600793
申请日：2008-05-16
申请人： Satoru Fujii , Yoshihiko Kanzawa , Takeshi Takagi , Kazuhiko Shimakawa
发明人： Satoru Fujii , Yoshihiko Kanzawa , Takeshi Takagi , Kazuhiko Shimakawa
IPC分类号： H01L45/00
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/1625
摘要： A nonvolatile semiconductor apparatus of the present invention comprises (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), a resistance value of the resistance variable layer being switchable reversibly in response to an electric signal applied between the electrodes (103), (105), wherein the resistance variable layer (104) comprises an oxide containing tantalum and nitrogen.
摘要翻译：本发明的非易失性半导体装置包括：（103），设置在第一电极（103）和第二电极（105）之间的第二电极（105）和电阻变化层（104），电阻值可变层可响应施加在电极（103），（105）之间的电信号而可逆地切换，其中电阻变化层（104）包括含有钽和氮的氧化物。

86. 发明授权

US08102696B2 Nonvolatile memory device and method of writing data to nonvolatile memory device 有权
标题翻译：非易失性存储器件和将数据写入非易失性存储器件的方法
公开(公告)号：US08102696B2
公开(公告)日：2012-01-24
申请号：US12677421
申请日：2008-08-25
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： A nonvolatile memory device (300) is provided, including a memory cell array having plural resistance variable elements which are switchable between plural resistance states in response to electric pulses with the same polarity. A series resistance setting unit (310) is provided between the memory cell array (70) and an electric pulse application unit (50). The series resistance setting unit is controlled to change a resistance value of a series current path with a predetermined range with time in at least one of a case where the selected resistance variable element is switched from a low-resistance state to a high-resistance state and a case where the selected resistance variable element is switched from the high-resistance state to the low-resistance state.
摘要翻译：提供了一种非易失性存储器件（300），包括具有多个电阻可变元件的存储单元阵列，该电阻可变元件可响应于具有相同极性的电脉冲在多个电阻状态之间切换。在存储单元阵列（70）和电脉冲施加单元（50）之间设置串联电阻设定单元（310）。串联电阻设定单元被控制为在所选择的电阻可变元件从低电阻状态切换到高电阻状态的情况中的至少一个中随时间改变具有预定范围的串联电流路径的电阻值以及所选择的电阻可变元件从高电阻状态切换到低电阻状态的情况。

87. 发明授权

US08094481B2 Resistance variable memory apparatus 有权
标题翻译：电阻变量存储装置
公开(公告)号：US08094481B2
公开(公告)日：2012-01-10
申请号：US12529103
申请日：2008-03-12
申请人： Yoshikazu Katoh , Kazuhiko Shimakawa
发明人： Yoshikazu Katoh , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C8/08 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/74 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (10) of the present invention comprises a resistance variable element (1) which is switched to a high-resistance state when a voltage exceeds a first voltage and is switched to a low-resistance state when the voltage exceeds a second voltage, a controller (4), a voltage restricting active element (2) which is connected in series with the resistance variable element (1); and a current restricting active element which is connected in series with the resistance variable element (1) via the voltage restricting active element (2), and the controller (4) is configured to control the current restricting active element (3) so that a product of a current and a first resistance value becomes a first voltage or larger and to control the voltage restricting active element (2) so that the voltage between electrodes becomes smaller than a second voltage when the element is switched to the high-resistance state, while the controller (4) is configured to control the current restricting active element (3) so that an absolute value of a product of the current and the second resistance value becomes the second voltage or larger and an absolute value of a product of the current and the first resistance value becomes smaller than the first voltage, when the element is switched to the low-resistance state.
摘要翻译：本发明的电阻可变存储装置（10）具有电阻可变元件（1），当电压超过第一电压时，电阻可变元件（1）被切换到高电阻状态，当电压超过第二电压，控制器（4），与电阻可变元件（1）串联连接的电压限制有源元件（2）; 和电流限制有源元件（1）经由电压限制有源元件（2）与电阻可变元件（1）串联连接的电流限制有源元件，并且控制器（4）被配置为控制电流限制有源元件（3），使得电流和第一电阻值的乘积变为第一电压或更大，并且当元件切换到高电阻状态时，控制电压限制有源元件（2）使得电极之间的电压变得小于第二电压，而控制器（4）被配置为控制电流限制有源元件（3），使得电流和第二电阻值的乘积的绝对值变为第二电压或更大，并且电流的乘积的绝对值并且当元件切换到低电阻状态时，第一电阻值变得小于第一电压。

88. 发明授权

US07965539B2 Nonvolatile memory element, nonvolatile semiconductor memory apparatus, and reading method and writing method therefor 有权
标题翻译：非易失性存储元件，非易失性半导体存储器件及其读取方法和写入方法
公开(公告)号：US07965539B2
公开(公告)日：2011-06-21
申请号：US12516703
申请日：2008-09-25
申请人： Koichi Osano , Shunsaku Muraoka , Satoru Fujii , Kazuhiko Shimakawa
发明人： Koichi Osano , Shunsaku Muraoka , Satoru Fujii , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C7/1006 , G11C13/0007 , G11C2013/0076 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A nonvolatile memory element (101) of the present invention includes a resistance variable layer (112) which intervenes between a first electrode (111) and a second electrode (113) and is configured to include at least an oxide of a metal element of VI group, V group or VI group, and when an electric pulse of a specific voltage is applied between the first voltage (111) and the second voltage (113), the resistance variable layer is turned to have a first high-resistance state or a second high-resistance state in which its resistance value is a high-resistance value RH, or a low-resistance state in which its resistance value is a low-resistance value RL.
摘要翻译：本发明的非易失性存储元件（101）包括介于第一电极（111）和第二电极（113）之间的电阻变化层（112），并且被配置为至少包含VI的金属元素的氧化物组，V组或VI组，并且当在第一电压（111）和第二电压（113）之间施加特定电压的电脉冲时，电阻变化层转为具有第一高电阻状态或其电阻值为高电阻值RH的第二高电阻状态或其电阻值为低电阻值RL的低电阻状态。

89. 发明申请

US20110110144A1 WRITING METHOD FOR VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器元件的写入方法和可变电阻非易失性存储器件
公开(公告)号：US20110110144A1
公开(公告)日：2011-05-12
申请号：US13001905
申请日：2010-06-08
申请人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/21
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/56 , G11C2213/79
摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).
摘要翻译：提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有最大电阻值。在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻元件从低电阻状态（S52）到高电阻状态（S53）。

90. 发明授权

US07920408B2 Resistance change nonvolatile memory device 有权
标题翻译：电阻变化非易失性存储器件
公开(公告)号：US07920408B2
公开(公告)日：2011-04-05
申请号：US12513914
申请日：2008-06-20
申请人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii , Yoshihiko Kanzawa
发明人： Ryotaro Azuma , Kazuhiko Shimakawa , Satoru Fujii , Yoshihiko Kanzawa
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77 , H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).
摘要翻译：存储单元（MC）形成在沿X方向延伸的位线（BL）和在Y方向上延伸的字线（WL）的交点处。在Y方向并排配置有分别形成为在Z方向排列的一组位线（BL）的字线（WL）的多个基本阵列平面。在每个基本阵列平面中，偶数层中的位线和奇数层中的位线共同单独连接。每个选择开关元件（101至104）控制共用连接偶数层位线与全局位线（GBL）之间的电连接/非连接的切换，并且每个选择开关元件（111至114）控制切换共同连接的奇数位位线和全局位线（GBL）之间的连接/非连接。

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