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81. 发明授权

US09935001B2 Methods of forming an integrated circuit chip having two types of memory cells 有权
公开(公告)号：US09935001B2
公开(公告)日：2018-04-03
申请号：US15380936
申请日：2016-12-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhon Jhy Liaw
IPC分类号： H01L21/8238 , H01L21/768 , G11C11/419 , H01L27/11 , G11C5/06 , H01L23/528 , H01L23/532 , H01L23/522 , H01L27/092
CPC分类号： H01L21/76816 , G11C5/063 , G11C11/419 , H01L21/823821 , H01L21/823871 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53228 , H01L23/53257 , H01L27/0924 , H01L27/1104 , H01L27/1116
摘要： An integrated circuit chip includes a first type memory cell and a second type memory cell. The first type memory cell includes a first reference line landing pad and a first word line landing pad. The first reference line landing pad of the first type memory cell and the first word line landing pad of the first type memory cell are aligned along a first direction. The second type memory cell includes a first reference line segment extending along the first direction and a first word line landing pad. The first word line landing pad of the second type memory cell and the first reference line segment of the second type memory cell are spaced apart along a second direction different from the first direction.

82. 发明授权

US09916893B2 Dual-port SRAM connection structure 有权
公开(公告)号：US09916893B2
公开(公告)日：2018-03-13
申请号：US15714355
申请日：2017-09-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhon Jhy Liaw
IPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , H01L27/11
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , G11C11/4125 , H01L27/11
摘要： The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (PD-11 and PD-12) of the first inverter; and a second contact feature contacting second two pull-down devices (PD-21 and PD-22) of the second inerter.

83. 发明授权

US09893059B2 ROM chip manufacturing structures 有权
公开(公告)号：US09893059B2
公开(公告)日：2018-02-13
申请号：US15216470
申请日：2016-07-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhon Jhy Liaw
IPC分类号： G11C17/00 , H01L27/088 , G11C17/08 , H01L21/768 , H01L23/528 , H01L23/522 , G11C5/06 , H01L27/112 , H01L29/78
CPC分类号： H01L27/088 , G11C5/063 , G11C17/08 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L27/11226 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.

84. 发明授权

US09865349B2 Memory cell 有权
公开(公告)号：US09865349B2
公开(公告)日：2018-01-09
申请号：US15225642
申请日：2016-08-01
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhon Jhy Liaw
IPC分类号： G11C15/04 , H01L27/105 , H01L23/528 , H01L23/522 , H01L27/02 , H01L27/088
CPC分类号： G11C15/04 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/0886 , H01L27/1052 , H01L2924/0002 , H01L2924/00
摘要： Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh.

85. 发明申请

US20170301394A1 SRAM Structure with Reduced Capacitance and Resistance 审中-公开
公开(公告)号：US20170301394A1
公开(公告)日：2017-10-19
申请号：US15641013
申请日：2017-07-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhon Jhy Liaw
IPC分类号： G11C11/412 , H01L27/11 , H01L27/02
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/1104
摘要： A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.

86. 发明授权

US09711535B2 Method of forming FinFET channel 有权
公开(公告)号：US09711535B2
公开(公告)日：2017-07-18
申请号：US14658023
申请日：2015-03-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Hao Wang , Ching-Wei Tsai , Kuo-Cheng Ching , Jhon Jhy Liaw , Wai-Yi Lien
IPC分类号： H01L21/762 , H01L21/20 , H01L21/31 , H01L23/544 , H01L27/12 , H01L21/84 , H01L21/02 , H01L29/10 , H01L21/8234 , H01L29/78 , H01L29/06
CPC分类号： H01L27/1211 , H01L21/02236 , H01L21/02532 , H01L21/76264 , H01L21/823431 , H01L21/845 , H01L23/544 , H01L29/1037 , H01L29/1079 , H01L29/1083 , H01L29/66795 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453
摘要： A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.

87. 发明授权

US09620510B2 Stacked metal layers with different thicknesses 有权
公开(公告)号：US09620510B2
公开(公告)日：2017-04-11
申请号：US14969730
申请日：2015-12-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Jhon Jhy Liaw
IPC分类号： H01L27/11 , H01L29/78 , H01L27/02 , H01L27/108
CPC分类号： H01L27/1104 , H01L23/5286 , H01L27/0207 , H01L27/10826 , H01L27/10879 , H01L29/7851
摘要： A semiconductor chip includes a plurality of stacked conductive layers. The plurality of stacked conductive layers includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is disposed on a first side of the second conductive layer. The third conductive layer is disposed on a second side of the second conductive layer. The third conductive layer is disposed on a side of the second conductive layer. The second conductive layer has a thickness which is thicker than those of the first conductive layer and the third conductive layer.

88. 发明授权

US09607685B2 Memory array with strap cells 有权
公开(公告)号：US09607685B2
公开(公告)日：2017-03-28
申请号：US14813185
申请日：2015-07-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Jhon Jhy Liaw
IPC分类号： G11C5/02 , G11C11/419
CPC分类号： G11C11/419 , G11C5/02 , G11C8/16 , G11C11/412 , H01L27/0207 , H01L27/1104
摘要： A memory array comprises a plurality of memory cells arranged in columns and rows. The memory array also comprises a plurality of first-type strap cells arranged in a row, wherein each first-type strap cell comprises a first-type well strap structure. The memory array further comprises a plurality of second-type strap cells arranged in a row. Each second-type strap cell comprises a second-type well strap structure. Each column of memory cells is bracketed by at least one first-type strap cell of the plurality of first-type strap cells or at least one second-type strap cell of the plurality of second-type strap cells.

89. 发明授权

US09595475B2 Multi-stage fin formation methods and structures thereof 有权
标题翻译：多级翅片形成方法及其结构
公开(公告)号：US09595475B2
公开(公告)日：2017-03-14
申请号：US14556908
申请日：2014-12-01
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Jhon Jhy Liaw
IPC分类号： H01L21/8234 , H01L21/308 , H01L29/66 , H01L27/088 , H01L29/06
CPC分类号： H01L21/823431 , H01L21/3086 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/6656
摘要： A method for fabricating a semiconductor device having a multi-stage fin profile includes providing a substrate and forming a first spacer having a first spacer width over the substrate. The first spacer masks a first portion of the substrate during a first etch process. By way of example, the first etch process is performed on the substrate to form a first-stage fin region, where a width of the first-stage fin region is substantially equal to about the first spacer width. A second spacer having a second spacer width is formed over the substrate, where the second spacer and the first-stage fin region mask a second portion of the substrate during a second etch process. In some examples, the second etch process is performed on the substrate to form a second-stage fin region, where a width of the second-stage fin region is greater than the width of the first-stage fin region.
摘要翻译：一种制造具有多级翅片轮廓的半导体器件的方法包括提供衬底并形成在衬底上具有第一间隔物宽度的第一间隔物。在第一蚀刻工艺期间，第一间隔物掩盖衬底的第一部分。作为示例，在衬底上执行第一蚀刻工艺以形成第一级鳍片区域，其中第一级鳍片区域的宽度基本上等于第一间隔物宽度。具有第二间隔物宽度的第二间隔物形成在衬底上，其中在第二蚀刻工艺期间第二间隔物和第一段鳍区域掩盖衬底的第二部分。在一些示例中，在衬底上执行第二蚀刻工艺以形成第二级鳍片区域，其中第二级鳍片区域的宽度大于第一级鳍片区域的宽度。

90. 发明授权

US09418991B2 ROM chip manufacturing structures 有权
公开(公告)号：US09418991B2
公开(公告)日：2016-08-16
申请号：US14829293
申请日：2015-08-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhon Jhy Liaw
IPC分类号： H01L27/088 , H01L21/768 , H01L23/528 , H01L23/522 , G11C5/06 , H01L27/112 , G11C17/08 , H01L29/78
CPC分类号： H01L27/088 , G11C5/063 , G11C17/08 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L27/11226 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.

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