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81. 发明申请

US20090085027A1 THREE DIMENSIONAL STRAINED QUANTUM WELLS AND THREE DIMENSIONAL STRAINED SURFACE CHANNELS BY GE CONFINEMENT METHOD 有权
标题翻译：通过三维尺寸应变量子阱和三维应变表面通道
公开(公告)号：US20090085027A1
公开(公告)日：2009-04-02
申请号：US11864963
申请日：2007-09-29
申请人： Been-Yih Jin , Robert S. Chau , Brian S. Doyle , Jack T. Kavalieros
发明人： Been-Yih Jin , Robert S. Chau , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L29/12 , H01L21/205
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L29/0673 , H01L29/1054 , H01L29/66818 , H01L29/7851
摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

82. 发明授权

US07821061B2 Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications 有权
标题翻译：用于逻辑和多级存储器应用的硅锗和锗多重和纳米线结构
公开(公告)号：US07821061B2
公开(公告)日：2010-10-26
申请号：US11729565
申请日：2007-03-29
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/00
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译：一种提供晶体管或存储单元结构的方法。该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

83. 发明授权

US07485536B2 Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers 有权
标题翻译：通过原子层外延原位δ掺杂掺杂剂扩散阻挡层的突变结形成
公开(公告)号：US07485536B2
公开(公告)日：2009-02-03
申请号：US11326178
申请日：2005-12-30
申请人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
发明人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
IPC分类号： H01L21/335
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
摘要翻译：一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及衬底的阱和沟道区之间的阻挡层。

84. 发明申请

US20100248209A1 Three-dimensional integrated circuit for analyte detection 审中-公开
标题翻译：用于分析物检测的三维集成电路
公开(公告)号：US20100248209A1
公开(公告)日：2010-09-30
申请号：US11478335
申请日：2006-06-30
申请人： Suman Datta , Shriram Ramanathan , Jack T. Kavalieros , Justin K. Brask , Brandon Barnett
发明人： Suman Datta , Shriram Ramanathan , Jack T. Kavalieros , Justin K. Brask , Brandon Barnett
IPC分类号： G01R27/28 , H01L29/78 , H01L29/66 , H01L21/28 , G01N27/00 , C12Q1/70 , C12Q1/02 , G01N33/92 , G01N33/00 , G01N33/53 , G01N33/68
CPC分类号： G01N27/4145 , G01N27/4146 , Y10T436/143333
摘要： The embodiments of the invention relate to a device having a first substrate comprising a transistor; a second substrate; an insulating layer in between and adjoining the first and second substrates; and an opening within the second substrate, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening. Other embodiments relate to a method including providing a substrate comprising a first part, a second part, and an insulating layer in between and adjoining the first and second parts; fabricating a transistor on the first part; and fabricating an opening within the second part, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening.
摘要翻译：本发明的实施例涉及具有包括晶体管的第一衬底的器件; 第二基板; 位于第一和第二基板之间并邻接第一和第二基板的绝缘层; 以及在所述第二基板内的开口，所述开口与所述晶体管对准; 其中所述晶体管被配置为检测所述开口内的电荷变化。其他实施例涉及一种方法，包括提供在第一和第二部分之间并与之相邻的第一部分，第二部分和绝缘层的基底; 在第一部分制造晶体管; 以及在所述第二部分内制造开口，所述开口与所述晶体管对准; 其中所述晶体管被配置为检测所述开口内的电荷变化。

85. 发明授权

US07402856B2 Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same 有权
标题翻译：具有隔离元件以减轻边缘效应的非平面微电子器件及其制造方法
公开(公告)号：US07402856B2
公开(公告)日：2008-07-22
申请号：US11299102
申请日：2005-12-09
申请人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
发明人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.
摘要翻译：非平面微电子器件，制造器件的方法以及包括该器件的系统。所述非平面微电子器件包括：衬底主体，其包括衬底基座和鳍片，所述鳍片限定其顶部区域处的器件部分; 栅极电介质层，其在所述鳍片的两个横向相对的侧壁上以预定高度延伸，所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层，并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极，并进一步在栅介质层上延伸; 隔离元件，其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限，所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

86. 发明授权

US08785907B2 Epitaxial film growth on patterned substrate 有权
标题翻译：在图案化衬底上外延膜生长
公开(公告)号：US08785907B2
公开(公告)日：2014-07-22
申请号：US13722746
申请日：2012-12-20
申请人： Niti Goel , Niloy Mukherjee , Seung Hoon Sung , Van H. Le , Matthew V. Metz , Jack T. Kavalieros , Ravi Pillarisetty , Sanaz K. Gardner , Sansaptak Dasgupta , Willy Rachmady , Benjamin Chu-Kung , Marko Radosavljevic , Gilbert Dewey , Marc C. French , Jessica Kachian , Satyarth Suri , Robert S. Chau
发明人： Niti Goel , Niloy Mukherjee , Seung Hoon Sung , Van H. Le , Matthew V. Metz , Jack T. Kavalieros , Ravi Pillarisetty , Sanaz K. Gardner , Sansaptak Dasgupta , Willy Rachmady , Benjamin Chu-Kung , Marko Radosavljevic , Gilbert Dewey , Marc C. French , Jessica Kachian , Satyarth Suri , Robert S. Chau
IPC分类号： H01L29/06
CPC分类号： H01L21/764 , H01L21/02381 , H01L21/0245 , H01L21/02494 , H01L21/02507 , H01L21/02532 , H01L21/76232
摘要： An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.
摘要翻译：实施例包括将材料沉积到衬底上，其中材料包括与衬底（例如Si衬底上的III-V或IV外延（EPI）材料）不同的晶格常数。一个实施例包括形成在沟槽内的EPI层，其具有随着沟槽向上延伸而变窄的壁。实施例包括使用多个生长温度在沟槽内形成的EPI层。当温度变化时，在EPI层中形成的缺陷屏障在沟槽内和缺陷屏障之下包含缺陷。缺陷屏障之上和沟槽内的EPI层相对无缺陷。一个实施方案包括在沟槽内退火以引发缺陷湮灭的EPI层。一个实施例包括形成在沟槽内并覆盖有相对无缺陷的EPI层（仍包含在沟槽中）的EPI超晶格。本文描述了其它实施例。

87. 发明授权

US09711591B2 Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby 有权
公开(公告)号：US09711591B2
公开(公告)日：2017-07-18
申请号：US13997607
申请日：2011-12-28
申请人： Niloy Mukherjee , Matthew V. Metz , James M. Powers , Van H. Le , Benjamin Chu-Kung , Mark R. Lemay , Marko Radosavljevic , Niti Goel , Loren Chow , Peter G. Tolchinsky , Jack T. Kavalieros , Robert S. Chau
发明人： Niloy Mukherjee , Matthew V. Metz , James M. Powers , Van H. Le , Benjamin Chu-Kung , Mark R. Lemay , Marko Radosavljevic , Niti Goel , Loren Chow , Peter G. Tolchinsky , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/02 , H01L29/06
CPC分类号： H01L29/06 , H01L21/0237 , H01L21/0245 , H01L21/02455 , H01L21/02494 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02513 , H01L21/02532 , H01L21/02538 , H01L21/02587 , H01L21/0259 , H01L21/02617 , H01L21/02636 , H01L21/02658 , H01L21/02664
摘要： Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

88. 发明申请

US20160204037A1 INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON 有权
标题翻译：集成具有选择性外延生长和制造设备的VLSI兼容FIN结构
公开(公告)号：US20160204037A1
公开(公告)日：2016-07-14
申请号：US14777736
申请日：2013-06-28
申请人： Niti Goel , Ravi Pillarisetty , Willy Rachmady , Jack T. Kavalieros , Gilbert Dewey , Benjamin Chu-Kung , Marko Radosavljevic , Matthew V. Metz , Niloy Mukherjee , Robert S. Chau
发明人： Niti Goel , Ravi Pillarisetty , Willy Rachmady , Jack T. Kavalieros , Gilbert Dewey , Benjamin Chu-Kung , Marko Radosavljevic , Matthew V. Metz , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L21/8238 , H01L21/762 , H01L21/02
CPC分类号： H01L21/823807 , H01L21/0245 , H01L21/02455 , H01L21/02502 , H01L21/02532 , H01L21/02538 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L21/823431 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/267 , H01L29/66795
摘要： Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.
摘要翻译：通过从在浅沟槽隔离（STI）区域之间形成的第一沟槽的底部的衬底表面外延生长第一类型材料的第一外延区域，形成不同的n型和p型器件鳍。 STI区域和第一沟槽高度至少是其宽度的1.5倍。蚀刻掉STI区域以暴露衬底的顶表面以在第一外延区域之间形成第二沟槽。在第一外延区域的侧壁上的第二沟槽中形成间隔材料层。在第二外延区域之间的第二沟槽的底部的衬底表面生长第二类型材料的第二外延区域。可以从第一和第二外延区域形成正对和p型翅片对。翅片是共同整合的，并且从材料界面晶格失配减少缺陷。

89. 发明申请

US20140091361A1 METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING 有权
公开(公告)号：US20140091361A1
公开(公告)日：2014-04-03
申请号：US13631417
申请日：2012-09-28
申请人： Niti Goel , Ravi Pillarisetty , Niloy Mukherjee , Robert S. Chau , Willy Rachmady , Matthew V. Metz , Van H. Le , Jack T. Kavalieros , Marko Radosavljevic , Benjamin Chu-Kung , Gilbert Dewey , Seung Hoon Sung
发明人： Niti Goel , Ravi Pillarisetty , Niloy Mukherjee , Robert S. Chau , Willy Rachmady , Matthew V. Metz , Van H. Le , Jack T. Kavalieros , Marko Radosavljevic , Benjamin Chu-Kung , Gilbert Dewey , Seung Hoon Sung
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/0245 , H01L21/02538 , H01L21/823807 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/1054 , H01L29/1083 , H01L29/267 , H01L29/42392 , H01L29/66469 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/78696
摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

90. 发明申请

US20120193609A1 GERMANIUM-BASED QUANTUM WELL DEVICES 有权
标题翻译：基于锗的量子阱器件
公开(公告)号：US20120193609A1
公开(公告)日：2012-08-02
申请号：US13442098
申请日：2012-04-09
申请人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译：量子阱晶体管具有锗量子阱沟道区域。含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。通道区域上方和下方的分级硅锗层提高性能。多栅极电介质材料允许使用高k值栅极电介质。

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