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81. 发明申请

US20110059601A1 METHOD FOR TUNING A WORK FUNCTION OF HIGH-K METAL GATE DEVICES 有权
标题翻译：用于调谐高K金属栅极器件功能的方法
公开(公告)号：US20110059601A1
公开(公告)日：2011-03-10
申请号：US12944221
申请日：2010-11-11
申请人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/768 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within the first trench but not the second trench. A second metal layer and a third metal layer are formed in the first and second trenches. A thermal process is used to reflow the second metal layer and the third metal layer
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成第一沟槽和第二沟槽，并在第一和第二沟槽中形成第一金属层。然后至少部分地从第一沟槽内除去第一金属层而不是第二沟槽。在第一和第二沟槽中形成第二金属层和第三金属层。使用热处理来回流第二金属层和第三金属层

82. 发明授权

US07750416B2 Modifying work function in PMOS devices by counter-doping 失效
标题翻译：通过反掺杂改进PMOS器件的功能
公开(公告)号：US07750416B2
公开(公告)日：2010-07-06
申请号：US11416938
申请日：2006-05-03
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L29/76
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

83. 发明申请

US20100159685A1 Eliminating Poly Uni-Direction Line-End Shortening Using Second Cut 有权
标题翻译：使用二次切割消除多重单向线端缩短
公开(公告)号：US20100159685A1
公开(公告)日：2010-06-24
申请号：US12340113
申请日：2008-12-19
申请人： Harry Chuang , Kong-Beng Thei
发明人： Harry Chuang , Kong-Beng Thei
IPC分类号： H01L21/28
CPC分类号： H01L29/4238 , H01L21/823437 , H01L27/0207
摘要： A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening.
摘要翻译：形成集成电路结构的方法包括提供包括第一有源区和第二有源区的衬底; 在所述衬底上形成栅电极层; 并蚀刻栅电极层。栅极电极层的其余部分包括彼此基本平行的第一栅极条和第二栅极条; 以及不平行于并互连第一栅极条和第二栅极条的牺牲条。牺牲条在第一有源区和第二有源区之间。所述方法还包括形成覆盖所述第一栅极条和所述第二栅极条的部分的掩模层，其中所述牺牲条和所述第一栅极条和所述第二栅极条的部分通过所述掩模层中的开口暴露; 并且蚀刻所述牺牲条和所述第一栅极条和所述第二栅极条的所述部分通过所述开口。

84. 发明申请

US20100078695A1 Low Leakage Capacitors Including Portions in Inter-Layer Dielectrics 有权
标题翻译：包含部分电介质的低漏电容器
公开(公告)号：US20100078695A1
公开(公告)日：2010-04-01
申请号：US12331109
申请日：2008-12-09
申请人： Oscar M. K. Law , Kong-Beng Thei , Harry Chuang
发明人： Oscar M. K. Law , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate including a first region and a second region; an insulation region in the second region of the semiconductor substrate; and an inter-layer dielectric (ILD) over the insulation region. A transistor is in the first region. The transistor includes a gate dielectric and a gate electrode over the gate dielectric. A first conductive line and a second conductive line are over the insulation region. The first conductive line and the second conductive line are substantially parallel to each other and extending in a first direction. A first metal line and a second metal line are in a bottom metal layer (M1) and extending in the first direction. The first metal line and the second metal line substantially vertically overlap the first conductive line and the second conductive line, respectively. The first metal line and the second metal line form two capacitor electrodes of a capacitor.
摘要翻译：集成电路结构包括包括第一区域和第二区域的半导体衬底; 半导体衬底的第二区域中的绝缘区域; 和绝缘区域上的层间电介质（ILD）。晶体管处于第一区域。晶体管包括栅极电介质和位于栅极电介质上的栅电极。第一导线和第二导线在绝缘区上方。第一导线和第二导线基本上彼此平行并沿第一方向延伸。第一金属线和第二金属线位于底部金属层（M1）中并沿第一方向延伸。第一金属线和第二金属线分别基本上垂直地与第一导线和第二导线重叠。第一金属线和第二金属线形成电容器的两个电容器电极。

85. 发明申请

US20100068877A1 METHOD FOR TUNING A WORK FUNCTION OF HIGH-K METAL GATE DEVICES 有权
标题翻译：用于调谐高K金属栅极器件功能的方法
公开(公告)号：US20100068877A1
公开(公告)日：2010-03-18
申请号：US12488960
申请日：2009-06-22
申请人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底中形成第一和第二晶体管，第一晶体管具有包括第一虚拟栅极的第一栅极结构，第二晶体管具有第二栅极结构包括第二伪栅极，去除第一和第二伪栅极，从而分别形成第一沟槽和第二沟槽，形成第一金属层以部分地填充在第一和第二沟槽中，去除第一沟槽内的第一金属层形成第二金属层以部分地填充在第一和第二沟槽中，形成第三金属层以部分地填充在第一和第二沟槽中，回流第二金属层和第三金属层，以及形成第四金属层以填充在第一和第二个沟槽的剩余部分。

86. 发明申请

US20100065926A1 PHOTORESIST ETCH BACK METHOD FOR GATE LAST PROCESS 有权
标题翻译：用于门控最后过程的光电复归方法
公开(公告)号：US20100065926A1
公开(公告)日：2010-03-18
申请号：US12477618
申请日：2009-06-03
申请人： Chiung-Han Yeh , Chen-Pin Hsu , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Chen-Pin Hsu , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L29/78 , H01L21/283 , H01L21/336
CPC分类号： H01L29/42376 , H01L21/28079 , H01L21/28088 , H01L21/28105 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a portion of the trench, forming a protection layer in a remaining portion of the trench, removing a unprotected portion of the first metal layer, removing the protection layer from the trench, and forming a second metal layer over the substrate to fill the trench.
摘要翻译：提供了制造半导体器件的方法。该方法包括提供包括形成在其上的虚拟栅极结构的衬底，去除伪栅极结构以形成沟槽，在衬底上形成第一金属层以填充沟槽的一部分，在其中的一部分形成保护层去除所述第一金属层的未受保护部分，从所述沟槽移除所述保护层，以及在所述衬底上形成第二金属层以填充所述沟槽。

87. 发明申请

US20100013029A1 Structure and a Method of Manufacture for Low Resistance NiSix 有权
标题翻译：低电阻NiSix的结构和制造方法
公开(公告)号：US20100013029A1
公开(公告)日：2010-01-21
申请号：US12176133
申请日：2008-07-18
申请人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L29/4983 , H01L21/28518 , H01L21/28525 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.
摘要翻译：提出了一种用于形成金属硅化物的器件和方法。在基板上形成包括栅极区域，源极区域和漏极区域的器件。在基板上设置金属，接着进行第一退火，在栅极区域，源极区域和漏极区域中的至少一个上形成金属硅化物。将未反应的金属从基材上除去。金属硅化物被注入原子。植入物之后是衬底的超退火。

88. 发明申请

US20100001369A1 DEVICE LAYOUT FOR GATE LAST PROCESS 有权
标题翻译：上一个流程的设备布局
公开(公告)号：US20100001369A1
公开(公告)日：2010-01-07
申请号：US12471091
申请日：2009-05-22
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要： A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，形成在第二区域中的隔离结构，形成在隔离结构中的至少一个接合器件第二区域，以及形成在第二区域中的隔离结构上方的停止结构。

89. 发明申请

US20090298243A1 SOI DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译： SOI器件及其制造方法
公开(公告)号：US20090298243A1
公开(公告)日：2009-12-03
申请号：US12468131
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

90. 发明申请

US20090236633A1 SRAM Devices Utilizing Strained-Channel Transistors and Methods of Manufacture 有权
标题翻译：使用应变通道晶体管的SRAM器件和制造方法
公开(公告)号：US20090236633A1
公开(公告)日：2009-09-24
申请号：US12052389
申请日：2008-03-20
申请人： Harry Chuang , Hung-Chih Tsai , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L27/092
CPC分类号： H01L21/8238 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.
摘要翻译：提供了一种新颖的SRAM存储单元结构及其制造方法。 SRAM存储单元结构包括形成在半导体衬底中的应变PMOS晶体管。 PMOS晶体管包括导致显着的PMOS晶体管驱动电流增加的外延生长的源极/漏极区域。绝缘层形成在用于电隔离相邻PMOS晶体管的STI之上。绝缘层基本上从半导体衬底表面升高。升高的绝缘层有助于形成期望的厚的外延源/漏极区，并且由于在生长外延酸/漏区域的过程中由于外延层侧向延伸而防止相邻外延层之间的桥接。形成升高的绝缘层的处理步骤与传统的CMOS工艺流程兼容。

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