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81. 发明授权

US5495296A Digital signal processing circuit for filtering an image signal vertically 失效
标题翻译：用于垂直滤波图像信号的数字信号处理电路
公开(公告)号：US5495296A
公开(公告)日：1996-02-27
申请号：US59561
申请日：1993-05-12
申请人： Shiro Dosho , Tatsuro Juri
发明人： Shiro Dosho , Tatsuro Juri
IPC分类号： H04N5/14 , H03H17/00 , H04N7/00 , H04N7/46 , H04N9/804 , H04N9/808 , H04N9/87 , H04N11/04 , H04N11/16 , H04N11/22 , H04N19/00 , H04N19/423 , H04N19/426 , H04N19/59
CPC分类号： H04N19/59 , H04N11/22 , H04N9/8042 , H04N9/87
摘要： In order to thin an input signal a second multiplexer is switched to output an output of a first adder and a third multiplexer is switched to output an output of a second adder, and a first multiplexer is alternatively switched at every line. A delay circuit memorizes the sum of the two preceding input signals, and the second adder outputs at every other line the sum of image data of a present line and the two preceding lines. To interpolate an input signal, the second multiplexer is switched to output the output of the delay circuit, the first multiplexer is alternatively switched to output either the input signal or the output of the second multiplexer, and the second multiplexer is alternatively switched to output either the output of the first adder or the output of the delay circuit. Thus, the delay circuit outputs at every other line the sum of the two preceding input signals. Because only one delay circuit is needed the size of the perpendicular thinning/interpolation circuit for an image signal is reduced.
摘要翻译：为了使输入信号变薄，第二多路复用器被切换以输出第一加法器的输出，并且第三多路复用器被切换以输出第二加法器的输出，并且第一多路复用器在每一行交替切换。延迟电路存储前两个输入信号的和，并且第二加法器在每隔一行输出当前行和前两行的图像数据之和。为了插入输入信号，第二多路复用器被切换以输出延迟电路的输出，第一多路复用器被交替切换以输出第二多路复用器的输入信号或输出，并且第二多路复用器交替切换以输出第一加法器的输出或延迟电路的输出。因此，延迟电路在每隔一行输出前面两个输入信号的和。因为只需要一个延迟电路，所以减小图像信号的垂直细化/插值电路的尺寸。

82. 发明授权

US08604956B2 Resonator and oversampling A/D converter 有权
公开(公告)号：US08604956B2
公开(公告)日：2013-12-10
申请号：US13073335
申请日：2011-03-28
申请人： Shiro Dosho , Kazuo Matsukawa , Yosuke Mitani
发明人： Shiro Dosho , Kazuo Matsukawa , Yosuke Mitani
IPC分类号： H03M3/00
CPC分类号： H03M3/454 , H03H11/1252 , H03M3/404 , H03M3/438
摘要： Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.

83. 发明授权

US08466820B2 Oversampling A/D converter 有权
公开(公告)号：US08466820B2
公开(公告)日：2013-06-18
申请号：US13025666
申请日：2011-02-11
申请人： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
发明人： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
IPC分类号： H03M3/00
CPC分类号： H03M1/12 , H03M3/344 , H03M3/43 , H03M3/454
摘要： An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

84. 发明授权

US08258990B2 Integrator, resonator, and oversampling A/D converter 有权
标题翻译：积分器，谐振器和过采样A / D转换器
公开(公告)号：US08258990B2
公开(公告)日：2012-09-04
申请号：US12888126
申请日：2010-09-22
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
IPC分类号： H03M3/00
CPC分类号： H03M3/454 , H03M3/404 , H03M3/43
摘要： An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
摘要翻译：积分器包括运算放大器，连接到运算放大器的反相输入端的第一滤波器和连接在运算放大器的反相输入端和输出端之间的第二滤波器。第一滤波器包括串联连接的n个电阻元件和（n-1）个电容元件，每个电容元件的一端连接到电阻元件的互连节点，另一端连接到地。第二滤波器包括串联连接的n个电容元件和（n-1）个电阻元件，每个电阻元件的一端连接到电容元件的互连节点，另一端连接到地。

85. 发明授权

US08212624B2 Reference frequency generation circuit, semiconductor integrated circuit, and electronic device 有权
标题翻译：参考频率发生电路，半导体集成电路和电子设备
公开(公告)号：US08212624B2
公开(公告)日：2012-07-03
申请号：US13022029
申请日：2011-02-07
申请人： Yusuke Tokunaga , Shiro Sakiyama , Akinori Matsumoto , Shiro Dosho
发明人： Yusuke Tokunaga , Shiro Sakiyama , Akinori Matsumoto , Shiro Dosho
IPC分类号： H02K3/26
CPC分类号： H03K4/501
摘要： An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.
摘要翻译：响应于参考时钟的信号电平的转变，振荡器电路以互补的方式增加并降低第一和第二振荡信号的信号电平。振荡控制电路将第一和第二振荡信号的每个信号电平与比较电压进行比较，并根据比较结果使参考时钟的信号电平转变。参考控制电路增加或减小比较电压，使得与第一和第二振荡信号的相应摆动成比例的中间信号的信号电平与参考电压之间的差减小。

86. 发明授权

US08130608B2 Coupled ring oscillator and method for initializing the same 有权
标题翻译：耦合环形振荡器及其初始化方法
公开(公告)号：US08130608B2
公开(公告)日：2012-03-06
申请号：US12967498
申请日：2010-12-14
申请人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G11B7/00 , H03K3/03
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译：在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡固定状态，然后将q个逆变器电路的输出从同相固定状态解除。

87. 发明授权

US08040168B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US08040168B2
公开(公告)日：2011-10-18
申请号：US11188855
申请日：2005-07-26
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： H03L7/06 , G05F3/02
CPC分类号： H02M3/07
摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.
摘要翻译：电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。

88. 发明授权

US08013650B2 Phase adjustment circuit 有权
标题翻译：相位调整电路
公开(公告)号：US08013650B2
公开(公告)日：2011-09-06
申请号：US11514151
申请日：2006-09-01
申请人： Shiro Dosho , Shiro Sakiyama , Yusuke Tokunaga , Seiji Watanabe , Hiroshi Koshida
发明人： Shiro Dosho , Shiro Sakiyama , Yusuke Tokunaga , Seiji Watanabe , Hiroshi Koshida
IPC分类号： H03H11/16
CPC分类号： H03K5/13 , H03K5/15013 , H03K2005/00052 , H03K2005/00273
摘要： A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.
摘要翻译：相位调整电路包括第一至第二相位调整电路。每个两相调节电路包括用于执行两个输入信号的逻辑和的第一逻辑电路，用于执行两个输入信号的逻辑积的第二逻辑电路，具有等于第二逻辑电路的信号延迟的信号延迟的第一延迟电路并且被配置为延迟从第一逻辑电路输出的信号;以及第二延迟电路，其具有等于第一逻辑电路的信号延迟的信号延迟，并且被配置为延迟从第二逻辑电路输出的信号。在一定阶段从两相调节电路中输出的两个信号在下一级输入到两相调节电路之一。

89. 发明申请

US20110080821A1 COUPLED RING OSCILLATOR AND METHOD FOR INITIALIZING THE SAME 有权
标题翻译：耦合振荡器及其初始化方法
公开(公告)号：US20110080821A1
公开(公告)日：2011-04-07
申请号：US12967498
申请日：2010-12-14
申请人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G11B20/10 , H03K3/03
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译：在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡固定状态，然后将q个逆变器电路的输出从同相固定状态解除。

90. 发明授权

US07782112B2 Device and method for generating clock signal 有权
标题翻译：用于产生时钟信号的装置和方法
公开(公告)号：US07782112B2
公开(公告)日：2010-08-24
申请号：US12330947
申请日：2008-12-09
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Akinori Matsumoto
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Akinori Matsumoto
IPC分类号： G06F1/04
CPC分类号： H03K5/135 , H03K5/1565 , H03K23/54 , H03K2005/00241
摘要： In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector.
摘要翻译：在用于从输入多相时钟信号产生期望相位的时钟信号的装置中，中间时钟发生器通过使用输入多相时钟信号之一作为参考时钟信号来产生多相中间时钟信号哪个周期等于参考时钟信号的多个周期。第一相位选择器选择多相中间时钟信号之一。第二相位选择器选择多相时钟信号之一。锁存电路将由第一相位选择器选择的中间时钟信号与由第二相位选择器选择的时钟信号进行锁存。

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