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81. 发明申请

US20050164446A1 Method for manufacturing single-sided buried strap in semiconductor devices 有权
标题翻译：在半导体器件中制造单面埋入带的方法
公开(公告)号：US20050164446A1
公开(公告)日：2005-07-28
申请号：US10940761
申请日：2004-09-15
申请人： Shian-Jyh Lin , Chia-Sheng Yu
发明人： Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/306 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L21/8244
CPC分类号： H01L27/10867
摘要： A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface lower than a surface of the semiconductor substrate such that a recess is formed. Then, an insulative layer is formed on a sidewall of the recess. Next, impurities are implanted into a portion of the insulative layer, and the impurity-containing insulative layer is thereafter removed such that at least a portion of the contact surface and a portion of sidewall of the recess are exposed. A buried strap is sequentially formed on the exposed sidewall of the recess to be in contact with the exposed contact surface.
摘要翻译：公开了一种制造半导体器件中使用的单端掩埋带的方法。根据本发明，在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有比半导体衬底的表面低的接触表面，从而形成凹部。然后，在凹部的侧壁上形成绝缘层。接下来，将杂质注入到绝缘层的一部分中，然后去除含杂质的绝缘层，使得接触表面的至少一部分和凹部的侧壁的一部分露出。在凹部的暴露的侧壁上依次形成埋设的带子，以与暴露的接触表面接触。

82. 发明申请

US20130153982A1 SEMICONDUCTOR DEVICE CAPABLE OF REDUCING INFLUENCES OF ADJACENT WORD LINES OR ADJACENT TRANSISTORS AND FABRICATING METHOD THEREOF 有权
公开(公告)号：US20130153982A1
公开(公告)日：2013-06-20
申请号：US13325063
申请日：2011-12-14
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L27/088
CPC分类号： H01L29/792 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.

83. 发明授权

US08202801B1 Method of fabricating a semiconductor device with through substrate via 有权
标题翻译：制造具有贯通基板通孔的半导体器件的方法
公开(公告)号：US08202801B1
公开(公告)日：2012-06-19
申请号：US13400592
申请日：2012-02-21
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L21/44
CPC分类号： H01L23/481 , H01L21/76898 , H01L25/0657 , H01L2224/94 , H01L2225/06544 , H01L2924/01019 , H01L2924/09701
摘要： A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
摘要翻译：提供了具有低应力的贯通基板通孔。贯通基板通孔位于基板中。贯通基板通孔包括：穿过基板的外管; 设置在所述外管内的至少一个内管; 在外管的侧壁上衬有的电介质层和内管的侧壁; 填充内管的强度增强材料; 以及填充外管的导电层。

84. 发明申请

US20110260297A1 THROUGH-SUBSTRATE VIA AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：通过基底和其制造方法
公开(公告)号：US20110260297A1
公开(公告)日：2011-10-27
申请号：US12767808
申请日：2010-04-27
申请人： Shian-Jyh Lin , Shing-Hwa Renn
发明人： Shian-Jyh Lin , Shing-Hwa Renn
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L2224/05025 , H01L2224/05087 , H01L2224/05096 , H01L2224/05098 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/00
摘要： A method for fabricating a through-substrate via structure. A semiconductor substrate is provided. A first via hole is etched into the semiconductor substrate. A spacer is formed on sidewall of the first via hole. The semiconductor substrate is etched through the first via hole to form a second via hole. The second via hole is wet etched to form a bottle-shaped via hole. An insulating layer is formed lining a lower portion of the bottle-shaped via hole. A first conductive layer is deposited within the bottle-shaped via hole, wherein the first conductive layer define a cavity. A bond pad is formed on a front side of the semiconductor substrate, wherein the bond pad is electrically connected with the first conductive layer. A back side of the semiconductor substrate is polished to reveal the cavity. The cavity is filled with a second conductive layer.
摘要翻译：一种用于制造贯通基板通孔结构的方法。提供半导体衬底。第一通孔被蚀刻到半导体衬底中。间隔件形成在第一通孔的侧壁上。通过第一通孔蚀刻半导体衬底以形成第二通孔。第二通孔被湿蚀刻以形成瓶形通孔。在瓶状通孔的下部形成有绝缘层。第一导电层沉积在瓶形通孔内，其中第一导电层限定空腔。接合焊盘形成在半导体衬底的正面上，其中接合焊盘与第一导电层电连接。半导体衬底的背面被抛光以露出腔体。空腔填充有第二导电层。

85. 发明授权

US07923325B2 Deep trench device with single sided connecting structure and fabrication method thereof 有权
标题翻译：具有单面连接结构的深沟槽装置及其制造方法
公开(公告)号：US07923325B2
公开(公告)日：2011-04-12
申请号：US12573076
申请日：2009-10-02
申请人： Shian-Jyh Lin , Chien-Li Cheng
发明人： Shian-Jyh Lin , Chien-Li Cheng
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L27/10823 , H01L27/10867 , H01L29/66181
摘要： A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.
摘要翻译：具有单面连接结构的深沟槽装置。该装置包括其中具有沟槽的衬底。埋沟槽电容器设置在沟槽的下部。不对称环形绝缘体设置在沟槽的侧壁的上部。连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件项圈绝缘子。导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。盖层设置在连接结构上。还公开了一种深沟槽器件的制造方法。

86. 发明申请

US20100022065A1 DEEP TRENCH DEVICE WITH SINGLE SIDED CONNECTING STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：具有单面连接结构的深度加固装置及其制造方法
公开(公告)号：US20100022065A1
公开(公告)日：2010-01-28
申请号：US12573076
申请日：2009-10-02
申请人： Shian-Jyh Lin , Chien-LI Cheng
发明人： Shian-Jyh Lin , Chien-LI Cheng
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L27/10823 , H01L27/10867 , H01L29/66181
摘要： A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.
摘要翻译：具有单面连接结构的深沟槽装置。该装置包括其中具有沟槽的衬底。埋沟槽电容器设置在沟槽的下部。不对称环形绝缘体设置在沟槽的侧壁的上部。连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件项圈绝缘子。导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。盖层设置在连接结构上。还公开了一种深沟槽器件的制造方法。

87. 发明授权

US07592229B2 Method for fabricating a recessed-gate MOS transistor device 有权
标题翻译：凹陷栅极MOS晶体管器件的制造方法
公开(公告)号：US07592229B2
公开(公告)日：2009-09-22
申请号：US11460992
申请日：2006-07-30
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/223 , H01L21/28238 , H01L27/10876 , H01L29/4236 , H01L29/42376 , H01L29/66553
摘要： A method for fabricating a recessed-gate transistor is disclosed. A trench is recessed into a substrate. A poly/nitride spacer is formed on sidewalls of the trench. A trench bottom oxide is formed. The spacer is then stripped off. A source/drain doping region is formed on the exposed sidewalls of the trench in a self-aligned fashion. The trench bottom oxide is then stripped, thereby forming a curved gate channel.
摘要翻译：公开了一种用于制造凹陷栅极晶体管的方法。沟槽凹入基底。在沟槽的侧壁上形成多晶氮化物间隔物。形成沟底部氧化物。然后剥离间隔物。源/漏掺杂区域以自对准的方式形成在沟槽的暴露的侧壁上。然后去除沟底部氧化物，从而形成弯曲的栅极通道。

88. 发明申请

US20090146101A1 ETCHANT FOR METAL ALLOY HAVING HAFNIUM AND MOLYBDENUM 审中-公开
标题翻译：具有铪和钼的金属合金蚀刻剂
公开(公告)号：US20090146101A1
公开(公告)日：2009-06-11
申请号：US12103681
申请日：2008-04-15
申请人： Chih-Wei Huang , Chao-Sung Lai , Hsing-Kan Peng , Chung-Yuan Lee , Shian-Jyh Lin
发明人： Chih-Wei Huang , Chao-Sung Lai , Hsing-Kan Peng , Chung-Yuan Lee , Shian-Jyh Lin
IPC分类号： C09K13/08
CPC分类号： C23F1/26 , H01L21/32134
摘要： An etchant for etching a metal alloy having hafnium and molybdenum includes 20 to 80 percent by weight of nitric acid, 1 to 49 percent by weight of hydrofluoric acid, 1 to 96 percent by weight of sulfuric acid, and 1 to 30 percent by weight of water, based on the total weight of the etchant.
摘要翻译：用于蚀刻具有铪和钼的金属合金的蚀刻剂包括20至80重量％的硝酸，1至49重量％的氢氟酸，1至96重量％的硫酸和1至30重量％的水，基于蚀刻剂的总重量。

89. 发明申请

US20090104748A1 METHOD FOR FABRICATING SELF-ALIGNED RECESS GATE TRENCH 审中-公开
标题翻译：用于制造自对准的收缩门的方法
公开(公告)号：US20090104748A1
公开(公告)日：2009-04-23
申请号：US12049383
申请日：2008-03-17
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L21/20
CPC分类号： H01L29/66621 , H01L27/10867 , H01L27/10876 , H01L29/4236
摘要： A method for forming a recess gate trench includes a plurality of trench capacitors formed into a substrate having thereon a pad layer. A portion of the trench top oxide layer of each trench capacitor is etched away to form a hole. The hole is filled with a silicon layer that is coplanar with the pad layer. Shallow trench isolation (STI) structure is formed. A portion of the STI structure is etched away. The pad layer is then stripped. A spacer is formed on a sidewall of the silicon layer. A gate trench is then etched into the substrate in a self-aligned fashion.
摘要翻译：形成凹槽栅极沟槽的方法包括形成衬底的多个沟槽电容器，其上具有衬垫层。每个沟槽电容器的沟槽顶部氧化物层的一部分被蚀刻掉以形成孔。该孔填充有与衬垫层共面的硅层。形成浅沟槽隔离（STI）结构。 STI结构的一部分被蚀刻掉。然后剥去垫层。在硅层的侧壁上形成间隔物。然后以自对准的方式将栅极沟槽蚀刻到衬底中。

90. 发明申请

US20090065857A1 RAISED VERTICAL CHANNEL TRANSISTOR DEVICE 有权
标题翻译：放大的垂直通道晶体管器件
公开(公告)号：US20090065857A1
公开(公告)日：2009-03-12
申请号：US12265734
申请日：2008-11-06
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L29/78
CPC分类号： H01L21/823487 , H01L27/10876 , H01L29/66666
摘要： A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.
摘要翻译：提供一种用于制造垂直沟道晶体管器件的方法。在由衬垫氮化物层和衬垫氧化物层组成的电介质堆叠中形成开口。进行多个外延硅生长和干蚀刻工艺以在开口中形成漏极，垂直沟道和源极。随后，在垂直沟道上形成侧壁栅极电介质和侧壁栅电极。本发明适用于特别适用于非常高密度的沟槽电容器DRAM器件的动态随机存取存储器（DRAM）器件。

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