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81. 发明授权

US07099195B2 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices 有权
标题翻译：用于中和浮栅存储器单元和器件的隧道氧化物中的空穴的方法
公开(公告)号：US07099195B2
公开(公告)日：2006-08-29
申请号：US11217813
申请日：2005-09-01
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity.
摘要翻译：使用第一极性的源极电压的幅度的减小来中和浮栅存储器单元的隧道氧化物中的空穴的方法，以增加第二极性的控制栅极电压的幅度。

82. 发明授权

US07068543B2 Flash memory 失效
标题翻译：闪存
公开(公告)号：US07068543B2
公开(公告)日：2006-06-27
申请号：US11217825
申请日：2005-09-01
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.
摘要翻译：闪速存储器支持方法，用于使用第一极性的源极电压的幅度的减小来擦除存储器单元，以在擦除周期期间增加第二极性的控制栅极电压的幅度。

83. 发明授权

US07057932B2 Flash memory 失效
公开(公告)号：US07057932B2
公开(公告)日：2006-06-06
申请号：US11218855
申请日：2005-09-01
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

84. 发明授权

US07035145B2 Programming methods for multi-level flash EEPROMs 失效
公开(公告)号：US07035145B2
公开(公告)日：2006-04-25
申请号：US10998697
申请日：2004-11-29
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.

85. 发明申请

US20060046402A1 Flash cell structures and methods of formation 审中-公开
标题翻译：闪电池结构和形成方法
公开(公告)号：US20060046402A1
公开(公告)日：2006-03-02
申请号：US10930323
申请日：2004-08-31
申请人： Di Li , Chun Chen , Graham Wolstenholme , Sukesh Sandhu , Xianfeng Zhou
发明人： Di Li , Chun Chen , Graham Wolstenholme , Sukesh Sandhu , Xianfeng Zhou
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： Methods of fabrication and flash memory structures eliminate process steps while increasing capacitive coupling between floating gates and control gates of the memory cells. A thick floating gate is deposited early in the process, and a height and width of the floating gate is controlled with deposition and etching or the use of spacers.
摘要翻译：制造方法和闪存结构消除了工艺步骤，同时增加了浮动栅极和存储器单元的控制栅极之间的电容耦合。在该过程中早期沉积厚的浮栅，并且通过沉积和蚀刻或使用间隔物来控制浮栅的高度和宽度。

86. 发明申请

US20060008988A1 Method of forming a memory cell 审中-公开
标题翻译：形成存储单元的方法
公开(公告)号：US20060008988A1
公开(公告)日：2006-01-12
申请号：US11217944
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

87. 发明申请

US20060007750A1 Flash memory 有权
公开(公告)号：US20060007750A1
公开(公告)日：2006-01-12
申请号：US11219020
申请日：2005-09-01
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

88. 发明申请

US20060007749A1 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices 有权
公开(公告)号：US20060007749A1
公开(公告)日：2006-01-12
申请号：US11217952
申请日：2005-09-01
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity.

89. 发明申请

US20060007743A1 Flash memory 失效
公开(公告)号：US20060007743A1
公开(公告)日：2006-01-12
申请号：US11217825
申请日：2005-09-01
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

90. 发明申请

US20060007405A1 Adjustment apparatus 审中-公开
标题翻译：调整装置
公开(公告)号：US20060007405A1
公开(公告)日：2006-01-12
申请号：US10983652
申请日：2004-11-09
申请人： Chun Chen , Jing Zhang
发明人： Chun Chen , Jing Zhang
IPC分类号： G03B21/00
CPC分类号： H04N17/00 , G03B21/10 , G03B21/28
摘要： An adjustment apparatus comprises a base seat, sliding bracket and supporting stand, in which the lower surface of sliding bracket is contacted with the upper surface of the base seat and capable of being slid thereon. A mounting plate is installed at the upper end of the sliding bracket and a raised pin is projected on the surface of the mounting plate. The raised pin can be engaged with a rotating plate. A lens of an optical engine fixed and mounted on the surface of the rotating plate can be rotated levelly around the raised pin to do an adjustment to revise the rightward and leftward trapezoid deformation of an image projected on a screen. Besides, every kind of deformation can be revised by means of the multi-angles adjustment of a reflection mirror on the supporting stand installed at the front end of the sliding bracket.
摘要翻译：调节装置包括基座，滑动支架和支撑架，其中滑动支架的下表面与基座的上表面接触并能够在其上滑动。安装板安装在滑动支架的上端，凸起销突出在安装板的表面上。凸起的销可以与旋转板接合。固定并安装在旋转板的表面上的光学引擎的透镜可以围绕升高的销平稳地旋转，以进行调整，以修改投射在屏幕上的图像的向右和向左梯形变形。此外，可以通过安装在滑动支架前端的支撑架上的反射镜的多角度调整来修改各种变形。

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