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81. 发明授权

US07246224B2 System and method to enable platform personality migration 有权
标题翻译：系统和方法，实现平台人格迁移
公开(公告)号：US07246224B2
公开(公告)日：2007-07-17
申请号：US10951277
申请日：2004-09-27
申请人： Michael A. Rothman , Robert P. Hale , John P. Lambino , Mahesh S. Natu , Vincent J. Zimmer , Mohan J. Kumar
发明人： Michael A. Rothman , Robert P. Hale , John P. Lambino , Mahesh S. Natu , Vincent J. Zimmer , Mohan J. Kumar
IPC分类号： G06F15/177
CPC分类号： G06F9/4451 , Y10S707/99943
摘要： An embodiment of the present invention relates generally to computer configuration and, more specifically, to a system and method to seamlessly determine the component configurations of a series of heterogeneous platforms and enable their respective component configurations to be intelligently migrated from one platform to another. In some embodiments, the invention involves generating configuration binaries for a plurality of target platforms. The configuration binaries are used with tools to create configuration directives for the target machines. In at least one embodiment, the configuration directives are sent to the target platforms in a scripting language. In some embodiments, the scripts are automatically generated by a tool using the configuration binaries for various platforms and policy guidance to determine which settings should be set on or off. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及计算机配置，更具体地，涉及无缝地确定一系列异构平台的组件配置并且使得它们各自的组件配置能够从一个平台被智能迁移到另一个平台的系统和方法。在一些实施例中，本发明涉及为多个目标平台生成配置二进制文件。配置二进制文件与工具一起使用，以创建目标计算机的配置指令。在至少一个实施例中，配置指令以脚本语言发送到目标平台。在一些实施例中，脚本由工具自动生成，使用各种平台的配置二进制文件和策略指导来确定哪些设置应被设置为开或关。描述和要求保护其他实施例。

82. 发明授权

US07117396B2 Scalable CPU error recorder 失效
公开(公告)号：US07117396B2
公开(公告)日：2006-10-03
申请号：US10029308
申请日：2001-12-28
申请人： Eshwari P. Komarla , Suresh Marisetty , Mani Ayyar , Andrew J. Fish , Mohan J. Kumar , Shivnandan D. Kaushik
发明人： Eshwari P. Komarla , Suresh Marisetty , Mani Ayyar , Andrew J. Fish , Mohan J. Kumar , Shivnandan D. Kaushik
IPC分类号： G06F11/00
CPC分类号： G06F11/0787 , G06F11/073
摘要： A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.

83. 发明授权

US07000102B2 Platform and method for supporting hibernate operations 失效
公开(公告)号：US07000102B2
公开(公告)日：2006-02-14
申请号：US09895580
申请日：2001-06-29
申请人： Mohan J. Kumar , Shivnandan D. Kaushik , James B. Crossland , Linda J. Rankin , David J. O'Shea
发明人： Mohan J. Kumar , Shivnandan D. Kaushik , James B. Crossland , Linda J. Rankin , David J. O'Shea
IPC分类号： G06F9/445 , G06F1/26
CPC分类号： G06F1/30 , G06F1/3203 , G06F9/4418
摘要： One aspect of the invention relates to a method for supporting hibernation despite the presence of hot-plugged nodes and non-deterministic boot operations. The method comprises invoking a management interrupt in response to a Hibernate request. The management interrupt is used to obtain and store platform configuration information into a non-volatile storage location. The platform configuration information includes data to indicate whether a next boot sequence for a platform occurs as a deterministic boot sequence or a non-deterministic boot sequence as well as a boot node identifier and a listing of an order in which processors of the platform are initialized.

84. 发明授权

US06917999B2 Platform and method for initializing components within hot-plugged nodes 失效
标题翻译：在热插拔节点中初始化组件的平台和方法
公开(公告)号：US06917999B2
公开(公告)日：2005-07-12
申请号：US09895692
申请日：2001-06-29
申请人： Mohan J. Kumar , Shivnandan D. Kaushik , James B. Crossland , Linda J. Rankin , David J. O'Shea
发明人： Mohan J. Kumar , Shivnandan D. Kaushik , James B. Crossland , Linda J. Rankin , David J. O'Shea
IPC分类号： G06F9/445 , G06F9/50 , G06F13/00
CPC分类号： G06F9/5077 , G06F9/4411
摘要： One aspect of the invention relates to creation of a container object being part of software that is stored in platform readable medium and executed by a processor within a platform. The container comprises (i) a hardware identification object to identify to an operating system of the platform that a type of device represented by the container object is a node and (ii) a plurality of component objects to identify constituent components of the node. Another aspect of the invention is the distribution of BIOS to handle initiation of components of a substrate in response to hot-plug addition of that substrate.
摘要翻译：本发明的一个方面涉及作为存储在平台可读介质中并由平台内的处理器执行的软件的一部分的容器对象的创建。容器包括（i）用于向平台的操作系统识别由容器对象表示的设备的类型是节点的硬件标识对象，以及用于识别节点的组成部件的多个组件对象。本发明的另一方面是响应于该基板的热插入添加而分配BIOS以处理基板的部件的启动。

85. 发明授权

US10116750B2 Mechanism for highly available rack management in rack scale environment 有权
公开(公告)号：US10116750B2
公开(公告)日：2018-10-30
申请号：US15089377
申请日：2016-04-01
申请人： Mohan J. Kumar , Murugasamy K. Nachimuthu
发明人： Mohan J. Kumar , Murugasamy K. Nachimuthu
IPC分类号： G06F15/16 , H04L29/08 , H04L12/46 , H04L12/931 , H04L12/24 , H04L29/06
摘要： Methods and apparatus for highly available rack management in Rack Scale environment. Rack Management Modules (RMMs) are configured to manage power and thermal zones in a rack including a plurality of pooled system drawers, wherein each pooled system drawer is associated with a respective power zone including power sensors and power control devices and a respective thermal zone including thermal sensors and thermal devices. During operation, one of the RMMs is implemented as a master RMM, and the other is implemented as a slave RMM. The master RMM is used to monitor the power and thermal zones. State information is periodically synchronized between the master RMM and the slave RMM. The RMMs are further configured to perform a fail-over operation in connection with a failed or failing RMM, where after the fail-over operation the slave becomes the new master RMM and the previous master RMM becomes the new slave.

86. 发明申请

US20180077235A1 MECHANISM FOR DISAGGREGATED STORAGE CLASS MEMORY OVER FABRIC 审中-公开
公开(公告)号：US20180077235A1
公开(公告)日：2018-03-15
申请号：US15262473
申请日：2016-09-12
申请人： Murugasamy K. Nachimuthu , Mohan J. Kumar
发明人： Murugasamy K. Nachimuthu , Mohan J. Kumar
IPC分类号： H04L29/08 , H04L12/911
CPC分类号： H04L67/1097 , G06F3/06 , G06F12/00 , G06F13/00 , H04L47/70 , H04L49/00 , H04L67/02
摘要： Mechanisms for disaggregated storage class memory over fabric and associated methods, apparatus, and systems. A rack is populated with pooled system drawers including pooled compute drawers and pooled storage class memory (SCM) drawers, also referred to as SCM nodes. Optionally, a pooled memory drawer may include a plurality of SCM nodes. Each SCM node provides access to multiple storage class memory devices. Compute nodes including one or more processors and local storage class memory devices are installed in the pooled compute drawers, and are enabled to be selectively-coupled to access remote storage class memory devices over a low-latency fabric. During a memory access from an initiator node (e.g., a compute node) to a target node including attached disaggregated memory (e.g., an SCM node), a fabric node identifier (ID) corresponding to the target node is identified, and an access request is forwarded to that target node over the low-latency fabric. The memory access request is then serviced on the target node, and corresponding data is returned to the initiator. During compute node composition, the compute nodes are configured to access disaggregated memory resources in the SCM nodes.

87. 发明授权

US09829951B2 Enhanced system sleep state support in servers using non-volatile random access memory 有权
公开(公告)号：US09829951B2
公开(公告)日：2017-11-28
申请号：US13976901
申请日：2011-12-13
申请人： Mohan J. Kumar , Murugasamy K. Nachimuthu
发明人： Mohan J. Kumar , Murugasamy K. Nachimuthu
IPC分类号： G06F1/00 , G06F1/32 , G06F9/44
CPC分类号： G06F1/3206 , G06F1/3275 , G06F1/3287 , G06F9/4418 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.

88. 发明授权

US09342394B2 Secure error handling 有权
标题翻译：安全错误处理
公开(公告)号：US09342394B2
公开(公告)日：2016-05-17
申请号：US13997301
申请日：2011-12-29
申请人： Murugasamy Nachimuthu , Mohan J. Kumar , Theodros Yigzaw , Jose A. Vargas , Rajender Kuramkote
发明人： Murugasamy Nachimuthu , Mohan J. Kumar , Theodros Yigzaw , Jose A. Vargas , Rajender Kuramkote
IPC分类号： G06F11/00 , G06F11/07 , G06F11/36 , G06F21/57
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/3664 , G06F21/57
摘要： Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.
摘要翻译：本文描述了各种实施例。一些实施例包括操作系统和平台。该平台包括具有错误寄存器的处理器。操作系统只能通过平台以安全的方式（例如使用平台固件）写入错误寄存器。描述和要求保护其他实施例。

89. 发明授权

US09256493B2 Memory module architecture 有权
标题翻译：内存模块架构
公开(公告)号：US09256493B2
公开(公告)日：2016-02-09
申请号：US13993506
申请日：2011-12-28
申请人： Murugasamy K. Nachimuthu , Mohan J. Kumar , Debaleena Das , Dimitrios Ziakas
发明人： Murugasamy K. Nachimuthu , Mohan J. Kumar , Debaleena Das , Dimitrios Ziakas
IPC分类号： G06F11/10 , G11C5/04 , G11C13/00
CPC分类号： G06F11/1044 , G06F11/1064 , G11C5/04 , G11C13/0004
摘要： In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments.
摘要翻译：根据一些实施例，可以组织包含相变存储器元件的存储器模块，使得每个存储器集成电路都包括数据和纠错码。作为在每个集成电路中包括纠错码的结果，可以避免存储器模块提取错误校正码的额外访问，从而在一些实施例中提高整个存储器模块的性能。

90. 发明申请

US20150378841A1 Techniques to Communicate with a Controller for a Non-Volatile Dual In-Line Memory Module 有权
标题翻译：与非易失性双列直插式存储器模块的控制器进行通信的技术
公开(公告)号：US20150378841A1
公开(公告)日：2015-12-31
申请号：US14319361
申请日：2014-06-30
申请人： Sarathy Jayakumar , Mohan J. Kumar , Adam J. Brooks , George Vergis
发明人： Sarathy Jayakumar , Mohan J. Kumar , Adam J. Brooks , George Vergis
IPC分类号： G06F11/14 , G06F3/06 , G11C14/00 , G06F9/44
CPC分类号： G06F9/4401 , G06F11/1441 , G06F11/2015
摘要： Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.
摘要翻译：示例可以包括通过系统管理总线（SMBus）接口与用于非易失性双列直插存储器模块的控制器进行通信。在一些示例中，通过SMBus接口可访问的寄存器中保持的位的选择性断言可以实现与控制器的通信。选择性断言可以基于寄存器映射。

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