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81. 发明授权

US08108564B2 System and method for a configurable interface controller 有权
标题翻译：可配置接口控制器的系统和方法
公开(公告)号：US08108564B2
公开(公告)日：2012-01-31
申请号：US10697903
申请日：2003-10-30
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00
CPC分类号： G06F3/1423 , G06F3/1454 , G09G5/14 , G09G2360/121 , G09G2370/04
摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.
摘要翻译：灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。灵活的I / O接口以特定组件确定的速率从组件接收数据。然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。因此，保持与各个I / O控制器的接口。灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

82. 发明授权

US07953951B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07953951B2
公开(公告)日：2011-05-31
申请号：US12124396
申请日：2008-05-21
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

83. 发明授权

US07546393B2 System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups 失效
标题翻译：用于异步DMA命令完成通知的系统，其中包括标签的DMA命令属于多个标签组
公开(公告)号：US07546393B2
公开(公告)日：2009-06-09
申请号：US11695436
申请日：2007-04-02
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , Peichum Peter Liu , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , Peichum Peter Liu , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.
摘要翻译：本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

84. 发明申请

US20090083542A1 METHOD AND SYSTEM FOR CONTROLLED DISTRIBUTION OF APPLICATION CODE AND CONTENT DATA WITHIN A COMPUTER NETWORK 有权
标题翻译：用于计算机网络中应用代码和内容数据的控制分配的方法和系统
公开(公告)号：US20090083542A1
公开(公告)日：2009-03-26
申请号：US12325192
申请日：2008-11-29
申请人： David John Craft , Pradeep K. Dubey , Harm Peter Hofstee , James Allan Kahle
发明人： David John Craft , Pradeep K. Dubey , Harm Peter Hofstee , James Allan Kahle
IPC分类号： H04L9/00
CPC分类号： H04L63/0823 , H04L63/126 , H04L63/145 , H04L2463/102
摘要： A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.
摘要翻译：提出了一种安全的通信方法。客户端设备被配置为从由服务提供商操作的服务器下载应用代码和/或内容数据。嵌入在客户端中的是客户端私钥，客户端序列号和服务器公钥的副本。客户端形成请求，其中包括客户端序列号，使用服务器公钥加密请求，并将下载请求发送到服务器。服务器使用服务器的私钥对请求进行解密，并对客户端进行身份验证。接收到的客户端序列号用于搜索与嵌入式客户端私钥对应的客户端公钥。服务器将其响应（包括所请求的信息）与请求客户端的客户端公钥加密，并且只有请求客户端中的私钥可以用于解密从服务器下载的信息。

85. 发明授权

US07469332B2 Systems and methods for adaptively mapping an instruction cache 失效
标题翻译：用于自适应地映射指令高速缓存的系统和方法
公开(公告)号：US07469332B2
公开(公告)日：2008-12-23
申请号：US11070758
申请日：2005-03-02
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Harm Peter Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Harm Peter Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F9/355
CPC分类号： G06F12/0864
摘要： Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.
摘要翻译：公开了用于将系统存储器地址位自适应地映射到指令标签和到高速缓存中的索引的系统和方法。更具体地，公开了用于观察对于系统存储器位给定到标签和索引的映射而出现的冲突的硬件和软件。基于观察结果，可以确定最小化碰撞的最佳映射。

86. 发明申请

US20080307201A1 Method and Apparatus for Cooperative Software Multitasking In A Processor System with a Partitioned Register File 有权
标题翻译：具有分区寄存器文件的处理器系统中的协同软件多任务的方法和装置
公开(公告)号：US20080307201A1
公开(公告)日：2008-12-11
申请号：US11759636
申请日：2007-06-07
申请人： Brian Flachs , Harm Peter Hofstee , Brad William Michael
发明人： Brian Flachs , Harm Peter Hofstee , Brad William Michael
IPC分类号： G06F9/38 , G06F9/305
CPC分类号： G06F9/44526 , G06F9/30123 , G06F9/3851
摘要： A processor system executes multiple applet programs within a software application program in an information handling system. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In particular, the operating system software manages partitioning of a register file in the processor system to achieve a cooperative relationship among multiple applet programs within respective partitions of the register file. In one embodiment, the operating system software manages unique applet ID's to modify register file partition sizes and locations during applet program instruction text execution. In one embodiment, applet ID masking hardware provides sharing of register file space among multiple copies of applet program code.
摘要翻译：处理器系统在信息处理系统中的软件应用程序内执行多个小应用程序。信息处理系统包括在多任务环境中管理处理器系统硬件和软件的操作系统软件。特别地，操作系统软件管理处理器系统中的寄存器文件的分区，以实现在寄存器文件的相应分区内的多个小程序之间的协作关系。在一个实施例中，操作系统软件管理独特的小应用程序ID，以在小程序指令文本执行期间修改寄存器文件分区大小和位置。在一个实施例中，小应用程序ID屏蔽硬件提供小程序代码的多个副本之间的寄存器文件空间的共享。

87. 发明申请

US20080250414A1 Dynamically Partitioning Processing Across A Plurality of Heterogeneous Processors 失效
标题翻译：跨多个异构处理器的动态分区处理
公开(公告)号：US20080250414A1
公开(公告)日：2008-10-09
申请号：US12116628
申请日：2008-05-07
申请人： Daniel Alan Brokenshire , Harm Peter Hofstee , Barry L. Minor , Mark Richard Nutter
发明人： Daniel Alan Brokenshire , Harm Peter Hofstee , Barry L. Minor , Mark Richard Nutter
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.
摘要翻译：一个程序进入至少两个对象文件：一个对象文件，用于每个受支持的处理器环境。在编译过程中，将数据位置，计算强度和数据并行等代码特征分析并记录在目标文件中。在运行时间期间，代码特征与运行时考虑相结合，例如处理器上的当前负载和正在处理的数据的大小，以达到总体值。然后，总体值用于确定哪些处理器将被分配任务。这些值基于各种处理器的特性分配。例如，如果一个处理器更好地处理针对大量数据流的密集计算，则高度计算密集的程序和处理大量数据的程序对该处理器进行加权。然后在分配的处理器上加载和执行相应的对象。

88. 发明申请

US20080222394A1 Systems and Methods for TDM Multithreading 失效
标题翻译： TDM多线程的系统和方法
公开(公告)号：US20080222394A1
公开(公告)日：2008-09-11
申请号：US12124396
申请日：2008-05-21
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor David , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor David , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

89. 发明申请

US20080162877A1 Non-Homogeneous Multi-Processor System With Shared Memory 审中-公开
标题翻译：具有共享内存的非均匀多处理器系统
公开(公告)号：US20080162877A1
公开(公告)日：2008-07-03
申请号：US12049324
申请日：2008-03-15
申请人： Erik Richter Altman , Peter George Capek , Michael Karl Gschwind , Charles Ray Johns , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle , Sumedh W. Sathaye , John-David Wellman , Ravi Nair
发明人： Erik Richter Altman , Peter George Capek , Michael Karl Gschwind , Charles Ray Johns , Harm Peter Hofstee , Martin E. Hopkins , James Allan Kahle , Sumedh W. Sathaye , John-David Wellman , Ravi Nair
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： H04L63/168 , H04L67/10
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

90. 发明授权

US07174410B2 Method, apparatus and computer program product for write data transfer 失效
标题翻译：用于写入数据传输的方法，装置和计算机程序产品
公开(公告)号：US07174410B2
公开(公告)日：2007-02-06
申请号：US10418593
申请日：2003-04-17
申请人： Bernard Charles Drerup , Harm Peter Hofstee , Wendel Glenn Voigt , Barry Joe Wolford
发明人： Bernard Charles Drerup , Harm Peter Hofstee , Wendel Glenn Voigt , Barry Joe Wolford
IPC分类号： G06F13/40 , G06F13/42 , G06F13/20 , G06F13/14
CPC分类号： G06F13/4027
摘要： A first device is operable to communicate on an bus according to a first protocol. A bridge is also operable to communicate on the bus according to the first protocol. A second device is coupled to the bus via the bridge and operable to communicate according to a second protocol. The bridge has a memory for holding data received from the second device and is operable to translate from the second to the first protocol. The second device sends write data responsive to receiving a ready signal from the bridge, and includes memory for holding the write data that the second device has sent, but for which completion has not been signaled. The second device re-sends the write data from the memory responsive to receiving a non-completion signal via the bridge, and releases the memory for the data responsive to receiving a completion signal via the bridge.
摘要翻译：第一设备可操作以根据第一协议在总线上进行通信。桥接器还可操作以根据第一协议在总线上进行通信。第二设备经由桥耦合到总线并且可操作以根据第二协议进行通信。桥具有用于保存从第二设备接收的数据的存储器，并且可操作以从第二协议转换为第一协议。第二设备响应于从桥接收准备信号而发送写数据，并且包括用于保存第二设备已经发送的写入数据的存储器，但是还没有发出完成信号。响应于经由桥接器接收到非完成信号，第二设备从存储器重新发送写入数据，并且响应于经由桥接器接收完成信号而释放用于数据的存储器。

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