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81. 发明申请

US20160284723A1 3D Vertical NAND With III-V Channel 有权
标题翻译：具有III-V通道的3D垂直NAND
公开(公告)号：US20160284723A1
公开(公告)日：2016-09-29
申请号：US14666678
申请日：2015-03-24
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L27/115 , H01L27/06 , H01L29/788 , H01L29/201 , H01L29/16 , H01L23/528 , H01L29/51
CPC分类号： H01L27/11582 , H01L27/0605 , H01L27/1157 , H01L29/201 , H01L29/517 , H01L29/7926
摘要： Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.
摘要翻译：本文公开了具有III-V复合通道的垂直NAND串的3D存储器以及制造方法。 III-V族化合物具有至少一个III族元素和至少一个V族元素。 III-V化合物提供高电子迁移率晶体管电池。注意，与硅相比，III-V材料可能具有高得多的电子迁移率。因此，可以实现更高的电池电流和整体电池性能。此外，由于更高的载波移动性和速度，存储器件可能具有更好的读写效率。存储单元的隧道电介质可以具有与III-V NAND通道直接接触的Al 2 O 3膜。 NAND通道的漏极端可以是与金属区域直接接触的金属III-V合金。源极侧选择晶体管的主体可以由III-V族化合物或晶体硅形成。

82. 发明授权

US09449985B1 Memory cell with high-k charge trapping layer 有权
标题翻译：具有高k电荷捕获层的存储单元
公开(公告)号：US09449985B1
公开(公告)日：2016-09-20
申请号：US14721536
申请日：2015-05-26
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157 , H01L29/4234 , H01L29/513 , H01L29/517 , H01L29/7926
摘要： A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si3N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.
摘要翻译：公开了具有高k电荷存储区域的存储单元以及制造方法的非易失性存储装置。电荷存储区域具有三层或更多层介电材料。至少一层是高k材料。与Si 3 N 4相比，高k层具有更高的陷阱密度。电荷存储区域中的高k电介质增强了与存储单元通道的电容耦合，这可以提高存储单元电流，编程速度和擦除速度。电荷存储区具有高 - 低 - 高导带偏移，这可以改善数据保留。电荷存储区域具有低 - 高 - 低价带偏移，这可以改善擦除。

83. 发明授权

US09443865B2 Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel 有权
标题翻译：制造具有单片晶体硅垂直NAND通道的3D NAND存储器
公开(公告)号：US09443865B2
公开(公告)日：2016-09-13
申请号：US14575937
申请日：2014-12-18
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L21/02 , H01L21/324 , H01L27/115
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02532 , H01L21/02598 , H01L21/02603 , H01L21/0262 , H01L21/02653 , H01L21/324 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7827
摘要： Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are formed in horizontal layers of material above a substrate. A vertically-oriented NAND string is formed in each of the memory holes. Forming the vertically-oriented NAND string channel comprises growing monolithic crystalline silicon upwards in the memory hole from the substrate through all of the plurality of horizontal layers of material. Vapor phase epitaxial growth may be used grow the monolithic crystalline silicon upwards from the bottom of the vertically-oriented NAND channel. Alternatively, a nanowire of monolithic crystalline silicon is synthesized in the memory hole from the substrate at the bottom of the vertically-oriented NAND channel upwards to the top of the vertically-oriented NAND channel.
摘要翻译：这里公开了用于制造具有单晶硅半导体垂直NAND通道的3D NAND存储器件的技术。存储孔形成在衬底上方的水平材料层中。在每个存储器孔中形成垂直取向的NAND串。形成垂直取向的NAND串通道包括通过所有多个水平材料层在衬底的存储器孔中向上生长单片晶体硅。可以使用气相外延生长从垂直取向的NAND通道的底部向上生长单片晶体硅。或者，单片晶体硅的纳米线在垂直取向的NAND通道的底部的垂直取向的NAND通道的顶部的存储器孔中被合成。

84. 发明授权

US09443861B1 Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures 有权
标题翻译：用于三维记忆结构背面接触结构的氟阻隔绝缘垫片
公开(公告)号：US09443861B1
公开(公告)日：2016-09-13
申请号：US14723919
申请日：2015-05-28
申请人： SANDISK TECHNOLOGIES, INC.
发明人： Jayavel Pachamuthu , Ching-Huang Lu , Johann Alsmeier
IPC分类号： H01L21/8238 , H01L27/115
CPC分类号： H01L27/11524 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Electrical shorts caused by diffusion of residual fluorine in metallic layers can be retarded or eliminated by forming fluorine-blocking structures. A stack of alternating layers including electrically insulating layers and electrically conductive layers with a vertically extending trench is provided. In one embodiment, an insulating spacer can be formed by depositing a silicon nitride layer and partially or fully converting the silicon nitride layer into a silicon oxynitride layer, and by performing an anisotropic etch. Alternatively, an insulating spacer can be formed by forming a stack of a silicon nitride layer and a silicon oxide layer, and by performing an anisotropic etch. The silicon nitride layer or the silicon oxynitride layer can retard fluorine diffusion. Yet alternately, sidewalls of the electrically conductive layers can be nitrided to form metallic nitride portions that retard fluorine diffusion.
摘要翻译：通过形成氟阻断结构，可以延迟或消除由金属层中的残留氟扩散引起的电气短路。提供了包括电绝缘层和具有垂直延伸沟槽的导电层的交替层叠。在一个实施例中，可以通过沉积氮化硅层并且部分地或完全地将氮化硅层转化为氮氧化硅层并通过进行各向异性蚀刻来形成绝缘间隔物。或者，可以通过形成氮化硅层和氧化硅层的叠层并通过进行各向异性蚀刻来形成绝缘间隔物。氮化硅层或氮氧化硅层可以阻止氟扩散。或者，导电层的侧壁可以被氮化以形成延缓氟扩散的金属氮化物部分。

85. 发明授权

US09437606B2 Method of making a three-dimensional memory array with etch stop 有权
标题翻译：制造具有蚀刻停止的三维存储阵列的方法
公开(公告)号：US09437606B2
公开(公告)日：2016-09-06
申请号：US13933236
申请日：2013-07-02
申请人： SanDisk Technologies, Inc.
发明人： Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee , Masanori Terahara , Hirofumi Watatani , Jayavel Pachamuthu
IPC分类号： H01L29/792 , H01L27/115 , H01L21/822 , H01L27/06
CPC分类号： H01L27/11582 , H01L21/8221 , H01L27/0688 , H01L27/1157
摘要： A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成牺牲特征，通过具有蚀刻穿过材料的区域和在所述牺牲特征上具有蚀刻停止材料的蚀刻停止区域形成多个蚀刻，形成交替层在所述多个蚀刻通过区域和所述多个蚀刻停止区域之上的第一材料和第二材料，蚀刻所述堆叠以形成穿过所述堆叠并穿过所述蚀刻通过区域以暴露所述牺牲特征的多个开口，使得与叠层的第一和第二材料相比，优先蚀刻蚀刻材料，通过多个开口去除牺牲特征并蚀刻叠层以形成直到或仅部分地穿过蚀刻停止区域的狭缝沟槽，使得与蚀刻停止材料相比，优先蚀刻叠层的第一和第二材料。

86. 发明申请

US20160232985A1 Techniques for Determining Local Interconnect Defects 审中-公开
标题翻译：确定局部互连缺陷的技术
公开(公告)号：US20160232985A1
公开(公告)日：2016-08-11
申请号：US14712078
申请日：2015-05-14
申请人： SanDisk Technologies Inc.
发明人： Jagdish Sabde , Sagar Magia , Jayavel Pachamuthu
IPC分类号： G11C29/50 , G11C29/12 , G01R31/04 , G11C16/04
CPC分类号： G11C29/50 , G01R31/04 , G11C16/0408 , G11C16/0483 , G11C29/025 , G11C29/028 , G11C29/06 , G11C29/12 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006
摘要： Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.
摘要翻译：呈现了用于确定非易失性阵列中的缺陷的技术，特别是那些具有3D或BiCS类型的排列，其中NAND串相对于衬底在垂直方向上运行。在这种布置中，NAND串沿着存储器孔形成并连接到全局位线，并且通过垂直局部互连（例如用于源极线）分离成块或子块，并连接到相应的全局线。为了确定有缺陷的块，当施加高电压并且所有块被取消选择时，基于由局部互连抽取的电流量来确定参考电流。当所选择的块偏置于接地并且将高电压施加到互连时，确定泄漏电流的量。通过将参考电流与泄漏电流进行比较，可以确定所选择的块是否具有与局部互连结构相关的缺陷。

87. 发明申请

US20160181272A1 Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel 有权
标题翻译：制造具有单片晶体硅垂直NAND通道的3D NAND存储器
公开(公告)号：US20160181272A1
公开(公告)日：2016-06-23
申请号：US14575937
申请日：2014-12-18
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Jayavel Pachamuthu , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L27/115 , H01L21/324 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02532 , H01L21/02598 , H01L21/02603 , H01L21/0262 , H01L21/02653 , H01L21/324 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7827
摘要： Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are formed in horizontal layers of material above a substrate. A vertically-oriented NAND string is formed in each of the memory holes. Forming the vertically-oriented NAND string channel comprises growing monolithic crystalline silicon upwards in the memory hole from the substrate through all of the plurality of horizontal layers of material. Vapor phase epitaxial growth may be used grow the monolithic crystalline silicon upwards from the bottom of the vertically-oriented NAND channel. Alternatively, a nanowire of monolithic crystalline silicon is synthesized in the memory hole from the substrate at the bottom of the vertically-oriented NAND channel upwards to the top of the vertically-oriented NAND channel.
摘要翻译：这里公开了用于制造具有单晶硅半导体垂直NAND通道的3D NAND存储器件的技术。存储孔形成在衬底上方的水平材料层中。在每个存储器孔中形成垂直取向的NAND串。形成垂直取向的NAND串通道包括通过所有多个水平材料层在衬底的存储器孔中向上生长单片晶体硅。可以使用气相外延生长从垂直取向的NAND通道的底部向上生长单片晶体硅。或者，单片晶体硅的纳米线在垂直取向的NAND通道的底部的垂直取向的NAND通道的顶部的存储器孔中被合成。

88. 发明授权

US09356031B2 Three dimensional NAND string memory devices with voids enclosed between control gate electrodes 有权
标题翻译：具有封闭在控制栅电极之间的空隙的三维NAND串存储器件
公开(公告)号：US09356031B2
公开(公告)日：2016-05-31
申请号：US14456496
申请日：2014-08-11
申请人： SanDisk Technologies Inc.
发明人： Yao-Sheng Lee , Jayavel Pachamuthu , Raghuveer S. Makala , George Matamis , Johann Alsmeier , Henry Chien
IPC分类号： H01L27/115 , H01L29/66 , H01L29/788 , H01L21/764 , H01L29/06 , H01L29/51 , H01L29/423 , H01L21/28 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11524 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11582 , H01L29/0649 , H01L29/1033 , H01L29/42324 , H01L29/4234 , H01L29/513 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses.
摘要翻译：制造单片三维NAND串的方法包括在衬底上形成交替的第一和第二材料层的叠层，蚀刻叠层以形成前侧开口，通过前侧开口部分去除第二材料层以形成正面凹部，在前侧凹部中形成第一阻挡电介质，在前侧凹部中的第一阻挡电介质的上方形成电荷存储区域，在前侧开口的电荷存储区域上形成隧道介电层和半导体沟道，蚀刻堆叠以形成背侧开口，通过背侧开口移除第二材料层，以形成使用第一阻挡电介质作为蚀刻停止件的后侧凹槽，在后侧凹部中形成第二阻挡电介质，并在在后侧凹槽中的第二阻挡电介质。

89. 发明授权

US09230974B1 Methods of selective removal of blocking dielectric in NAND memory strings 有权
标题翻译：选择性去除NAND存储器串中的阻塞电介质的方法
公开(公告)号：US09230974B1
公开(公告)日：2016-01-05
申请号：US14468743
申请日：2014-08-26
申请人： SanDisk Technologies, Inc.
发明人： Jayavel Pachamuthu , Johann Alsmeier , George Matamis , Henry Chien
IPC分类号： H01L29/76 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/1157
摘要： Methods of making a monolithic three dimensional NAND string may enable selective removal of a blocking dielectric material, such as aluminum oxide, without otherwise damaging the device. Blocking dielectric may be selectively removed from the back side (e.g., slit trench) and/or front side (e.g., memory opening) of the NAND string. Also disclosed are NAND strings made in accordance with the embodiment methods.
摘要翻译：制造单片三维NAND串的方法可以使得能够选择性地去除阻挡电介质材料，例如氧化铝，而不会以其他方式损坏器件。可以从NAND串的背面（例如，狭缝沟槽）和/或前侧（例如，存储器开口）选择性地去除阻塞电介质。还公开了根据实施方式制造的NAND串。

90. 发明申请

US20150118811A1 METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS 有权
标题翻译：使用多层堆叠的顺序蚀刻制造垂直NAND器件的方法
公开(公告)号：US20150118811A1
公开(公告)日：2015-04-30
申请号：US14585912
申请日：2014-12-30
申请人： SANDISK TECHNOLOGIES INC.
发明人： Raghuveer S. Makala , Yao-Sheng Lee , Jayavel Pachamuthu , Johann Alsmeier , Henry Chien
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/822 , H01L21/8221 , H01L27/0688 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.
摘要翻译：制造垂直NAND器件的方法包括在衬底上形成存储器堆叠的下部，在存储堆的下部形成存储器开口的下部，并至少部分地填充存储器开口的下部，牺牲材料。该方法还包括在存储器堆叠的下部并在牺牲材料的上方形成存储器堆叠的上部，在存储器堆叠的上部形成存储器开口的上部部分，以将下部的牺牲材料露出部分存储器开口，去除牺牲材料以将存储器开口的下部与存储器开口的相应上部连接以形成连续的存储器开口，并在每个连续的存储器开口中形成半导体通道。

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