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    • 83. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20110127597A1
    • 2011-06-02
    • US13003644
    • 2009-07-01
    • Yoshiaki FukuzumiHiroyasu TanakaYosuke KomoriMegumi IshidukiMasaru KitoRyota KatsumataMasaru Kidoh
    • Yoshiaki FukuzumiHiroyasu TanakaYosuke KomoriMegumi IshidukiMasaru KitoRyota KatsumataMasaru Kidoh
    • H01L29/788H01L29/792
    • H01L29/7926G11C16/0466H01L27/11565H01L27/11578H01L27/11582
    • A nonvolatile semiconductor memory device with charge storage layers with high reliability is provided. A plurality of insulating films and a plurality of electrode films 14 are alternately stacked on a substrate 11, and a plurality of selection gate electrodes 17 extending in the X direction and a plurality of bit lines BL extending in the Y direction are provided thereon. U-shaped silicon members 33 are provided, each of which is constituted by a plurality of silicon pillars 31 passing through the electrode films 14 and the selection gate electrode 17, whose upper ends are connected to the bit lines BL, and a connective member 32 connecting lower parts of one pair of the silicon pillars 31 disposed in diagonal positions. The electrode film 14 of each layer is divided for the respective selection gate electrodes 17. One pair of the silicon pillars 31 connected to one another through the connective member 32 are caused to pass through the different electrode films 14 and the different selection gate electrodes 17. All of the U-shaped silicon members 33 connected commonly to one bit line BL are commonly connected to another bit line BL.
    • 提供具有高可靠性的电荷存储层的非易失性半导体存储器件。 多个绝缘膜和多个电极膜14交替堆叠在基板11上,并且在其上设置有沿X方向延伸的多个选择栅电极17和在Y方向上延伸的多个位线BL。 设置有U形硅构件33,每个都由通过电极膜14的多个硅柱31和其上端连接到位线BL的选择栅电极17构成,并且连接构件32 连接设置在对角位置的一对硅柱31的下部。 每个层的电极膜14被分配用于各个选择栅极电极17.使通过连接构件32彼此连接的一对硅柱31通过不同的电极膜14和不同的选择栅电极17 通常连接到一个位线BL的所有U形硅构件33共同连接到另一位线BL。
    • 84. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
    • 半导体存储器件及其制造方法
    • US20110215394A1
    • 2011-09-08
    • US12813895
    • 2010-06-11
    • Yosuke KomoriMasaru KidohRyota Katsumata
    • Yosuke KomoriMasaru KidohRyota Katsumata
    • H01L29/792H01L21/336
    • H01L27/11582G11C16/0483G11C16/26H01L27/0688H01L27/11573
    • According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines. The plurality of local bit lines are connected to the channel body and commonly connected to the global bit line through the contact plug.
    • 根据一个实施例,半导体存储器件包括基底,层叠体,存储膜,通道体,接触塞,全局位线和多个局部位线。 该基底具有形成于该基板上的基板和外围电路。 层叠体具有交替地堆叠在基底上的多个导电层和绝缘层。 记忆膜包括设置在层叠体的层叠方向形成的存储孔的内壁上的电荷存储膜。 通道体设置在存储器孔内的记忆膜的内部。 接触插塞是通过刺穿层叠体来提供的。 全局位线设置在外围电路和层叠体之间并连接到接触插塞的下端部分。 多个局部位线设置在堆叠体的上方并沿多个局部位线的延伸方向分割。 多个局部位线连接到通道体并且通过接触插塞共同连接到全局位线。
    • 85. 发明授权
    • Semiconductor memory device and method for manufacturing same
    • 半导体存储器件及其制造方法
    • US08288816B2
    • 2012-10-16
    • US12813895
    • 2010-06-11
    • Yosuke KomoriMasaru KidohRyota Katsumata
    • Yosuke KomoriMasaru KidohRyota Katsumata
    • H01L27/115
    • H01L27/11582G11C16/0483G11C16/26H01L27/0688H01L27/11573
    • According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines. The plurality of local bit lines are connected to the channel body and commonly connected to the global bit line through the contact plug.
    • 根据一个实施例,半导体存储器件包括基底,层叠体,存储膜,通道体,接触塞,全局位线和多个局部位线。 该基底具有形成于该基板上的基板和外围电路。 层叠体具有交替地堆叠在基底上的多个导电层和绝缘层。 记忆膜包括设置在层叠体的层叠方向形成的存储孔的内壁上的电荷存储膜。 通道体设置在存储器孔内的记忆膜的内部。 接触插塞是通过刺穿层叠体来提供的。 全局位线设置在外围电路和层叠体之间并连接到接触插塞的下端部分。 多个局部位线设置在堆叠体的上方并沿多个局部位线的延伸方向分割。 多个局部位线连接到通道体并且通过接触插塞共同连接到全局位线。
    • 88. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US08729623B2
    • 2014-05-20
    • US13423464
    • 2012-03-19
    • Tomo OhsawaYosuke Komori
    • Tomo OhsawaYosuke Komori
    • H01L29/792
    • H01L21/28282H01L27/11582H01L29/7926
    • According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction. Each of the plurality of electrode layers is a first semiconductor layer containing a first impurity element. The diffusion suppressing layer is a second semiconductor layer containing a second impurity element which is different from the first impurity element. The diffusion suppressing layer is a film having an effect of suppressing diffusion of the first impurity element.
    • 根据一个实施例,一种非易失性半导体存储器件包括:堆叠体,包括交替堆叠的多个电极层和多个绝缘层,以及分别设置在多个电极层中的每一个之间的扩散抑制层, 多个绝缘层; 以及设置在层叠方向上贯穿层叠体的孔的侧壁上的记忆膜。 多个电极层中的每一个是包含第一杂质元素的第一半导体层。 扩散抑制层是含有与第一杂质元素不同的第二杂质元素的第二半导体层。 扩散抑制层是具有抑制第一杂质元素扩散的效果的膜。