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81. 发明授权

US06378061B1 Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit 失效
标题翻译：用于通过使用延迟电路再循环来发出指令并再次发出先前指令的装置
公开(公告)号：US06378061B1
公开(公告)日：2002-04-23
申请号：US08150784
申请日：1993-11-12
申请人： Adrian Carbine , Glenn J. Hinton , Frank S. Smith
发明人： Adrian Carbine , Glenn J. Hinton , Frank S. Smith
IPC分类号： G06F930
CPC分类号： G06F9/3808 , G06F9/30054 , G06F9/3017 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： An instruction decoder that issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. This information is either extracted from the current instruction to be executed, or is recycled from the previous contents (106) of the machine bus when a scoreboarding operation has been performed. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes them to the machine bus (110) through several translation stages and multiplexers. The decision of which source to use is based on what kind of instruction is currently being looked at by the instruction queue in the instruction fetch unit. The instruction queue notifies the instruction decoder that the next instruction is to be either a RISC operation (including register, memory, and/or branch instructions) or an instruction which is part of a microcode flow. If a complex macroinstruction flow is in progress, its operands can be accessed through alias registers. This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100).
摘要翻译：一种指令解码器，其通过在每个时钟周期期间以正确的信息驱动机器总线（110）来发布新的指令。当执行记分操作时，该信息是从当前要执行的指令中提取的，或者从机器总线的先前内容（106）中循环回收的。捕鼠器多路复用器（104）在操作码和操作数字段的几个来源之间进行选择，并通过多个转换级和多路复用器将它们路由到机器总线（110）。使用哪个源的决定是基于指令提取单元中的指令队列当前正在查看什么样的指令。指令队列通知指令解码器下一条指令是RISC操作（包括寄存器，存储器和/或分支指令）或作为微代码流的一部分的指令。如果复杂的宏指令流正在进行，则可以通过别名寄存器访问其操作数。这允许在执行一个微指令序列时，间接访问由宏代码指令的操作数指定的源或目标寄存器或宏指令的操作码。这些混叠的操作数由宏指令混叠逻辑（100）维护。

82. 发明授权

US06230257B1 Method and apparatus for staggering execution of a single packed data instruction using the same circuit 失效
标题翻译：用于使用相同电路交错执行单个打包数据指令的方法和装置
公开(公告)号：US06230257B1
公开(公告)日：2001-05-08
申请号：US09053004
申请日：1998-03-31
申请人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
发明人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译：公开了一种用于交错执行指令的方法和装置。根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素。第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。

83. 发明授权

US5881262A Method and apparatus for blocking execution of and storing load operations during their execution 失效
标题翻译：用于在其执行期间阻止执行和存储加载操作的方法和装置
公开(公告)号：US5881262A
公开(公告)日：1999-03-09
申请号：US928924
申请日：1997-09-12
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/312 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3842
摘要： A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.
摘要翻译：一种用于在计算机系统中执行加载操作的方法和装置。本发明包括一种用于调度要执行的加载操作的方法和装置。本发明在加载操作和系统中当前待处理的另一个存储器操作之间存在依赖关系时，停止加载操作的执行。当依赖关系不再存在时，本发明重新分派加载操作使其完成。

84. 发明授权

US5845100A Dual instruction buffers with a bypass bus and rotator for a decoder of multiple instructions of variable length 失效
标题翻译：具有旁路总线和旋转器的双指令缓冲器，用于可变长度的多个指令的解码器
公开(公告)号：US5845100A
公开(公告)日：1998-12-01
申请号：US806022
申请日：1997-02-24
申请人： Ashwani Kumar Gupta , Glenn J. Hinton , Chan W. Lee
发明人： Ashwani Kumar Gupta , Glenn J. Hinton , Chan W. Lee
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30152 , G06F9/3816
摘要： A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.
摘要翻译：一种用于向指令解码器的指令缓冲器提供指令代码块的电路和方法。指令代码块通过缓冲器输入获取和输入。第一指令缓冲器和第二指令缓冲器耦合到缓冲器输入端以存储指令代码块。指令缓冲器的输出和耦合到缓冲器输入的旁路总线被输入到指令缓冲多路复用器。指令缓冲多路复用器在三个输入端之间进行选择，并向转子输出两个指令代码块。旋转器接收指示初始字节的输入指针。旋转器将从初始字节开始的指令代码块输出到指令解码器。

85. 发明授权

US5751996A Method and apparatus for processing memory-type information within a microprocessor 失效
标题翻译：用于处理微处理器内的存储器类型信息的方法和装置
公开(公告)号：US5751996A
公开(公告)日：1998-05-12
申请号：US767799
申请日：1996-12-17
申请人： Andrew F. Glew , Glenn J. Hinton
发明人： Andrew F. Glew , Glenn J. Hinton
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30043 , G06F12/0804 , G06F12/0888 , G06F9/3824 , G06F9/3842 , G06F9/3857
摘要： A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed in accordance with any one of a number of processing protocols including write-through processing, write-back processing, write-protect processing, restricted-cacheability processing, uncacheable speculatable write-combining processing, or uncacheable processing. By providing memory-type information explicitly within the microprocessor, the type of memory identified by a micro-instruction is known before the micro-instruction is processed. Accordingly, the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. For example, if the memory location identified by the micro-instruction is known to be uncacheable, a data cache unit is bypassed and external memory is accessed directly. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor capable of generating speculative memory micro-instruction. Also, the microprocessor may be only one of a number of microprocessors within a multiprocessor system.
摘要翻译：识别包含有存储器位置范围的存储器类型的存储器类型值被明确地存储在微处理器内。在处理诸如加载或存储之类的存储器微指令之前，为由存储器微指令识别的存储器位置确定存储器类型。一旦已知存储器类型，存储器微指令根据多种处理协议中的任何一种被处理，包括直写处理，回写处理，写保护处理，限制高速缓存处理，不可缓存的可写入写入 - 组合处理或不可缓解的处理。通过在微处理器内显式提供存储器类型信息，在微指令被处理之前，已经知道由微指令识别的存储器类型。因此，处理微指令的协议可以有效地针对存储器类型进行定制。例如，如果由微指令识别的存储器位置已知是不可缓存的，则旁路数据高速缓存单元，并直接访问外部存储器。在示例性实施例中，微处理器是能够产生推测存储器微指令的无序微处理器。此外，微处理器可能只是多处理器系统内的多个微处理器之一。

86. 发明授权

US5671444A Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers 失效
标题翻译：使用多个填充缓冲器以非阻塞方式高速缓存数据的方法和装置
公开(公告)号：US5671444A
公开(公告)日：1997-09-23
申请号：US731545
申请日：1996-10-15
申请人： Haitham Akkary , Jeffrey M. Abramson , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mandar S. Joshi , Brent E. Lince
发明人： Haitham Akkary , Jeffrey M. Abramson , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mandar S. Joshi , Brent E. Lince
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859 , G06F12/0831
摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.
摘要翻译：具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

87. 发明授权

US5608885A Method for handling instructions from a branch prior to instruction decoding in a computer which executes variable-length instructions 失效
标题翻译：用于在执行可变长度指令的计算机中的指令解码之前从分支处理指令的方法
公开(公告)号：US5608885A
公开(公告)日：1997-03-04
申请号：US205022
申请日：1994-03-01
申请人： Ashwani K. Gupta , Glenn J. Hinton , Chan W. Lee
发明人： Ashwani K. Gupta , Glenn J. Hinton , Chan W. Lee
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30152 , G06F9/3816
摘要： A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.
摘要翻译：一种用于向指令解码器的指令缓冲器提供指令代码块的电路和方法。指令代码块通过缓冲器输入获取和输入。第一指令缓冲器和第二指令缓冲器耦合到缓冲器输入端以存储指令代码块。指令缓冲器的输出和耦合到缓冲器输入的旁路总线被输入到指令缓冲多路复用器。指令缓冲多路复用器在三个输入端之间进行选择，并向转子输出两个指令代码块。旋转器接收指示初始字节的输入指针。旋转器将从初始字节开始的指令代码块输出到指令解码器。

88. 发明授权

US09378142B2 Apparatus and method for implementing a multi-level memory hierarchy having different operating modes 有权
标题翻译：用于实现具有不同操作模式的多级存储器层级的装置和方法
公开(公告)号：US09378142B2
公开(公告)日：2016-06-28
申请号：US13994731
申请日：2011-09-30
申请人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
发明人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
IPC分类号： G06F12/00 , G06F12/08 , G06F12/02 , G11C7/10 , G11C13/00
CPC分类号： G06F12/0811 , G06F12/0246 , G06F12/0806 , G06F12/0808 , G06F12/0815 , G06F12/0888 , G06F12/0893 , G06F2212/205 , G06F2212/283 , G06F2212/6046 , G06F2212/621 , G06F2212/7201 , G11C7/1045 , G11C7/1072 , G11C13/0004 , G11C14/0045
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
摘要翻译：描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。在一个实施例中，PCMS存储器件被用作层次结构中的一层，有时被称为“远存储器”。更高性能的存储器件例如放置在远存储器之前的DRAM，并用于掩盖某些性能限制远记忆这些更高性能的存储器件被称为“近存储器”。在一个实施例中，“近端存储器”被配置为以多种不同的操作模式操作，包括（但不限于）第一模式，其中近端存储器作为远存储器的存储器高速缓冲存储器和第二模式，其中近距离存储器被分配有系统地址空间的第一地址范围，远处存储器被分配系统地址空间的第二地址范围，其中第一范围和第二个范围代表整个系统地址空间。

89. 发明授权

US09146873B2 Adaptive queuing of a cache for a processing element 有权
标题翻译：用于处理元素的缓存的自适应排队
公开(公告)号：US09146873B2
公开(公告)日：2015-09-29
申请号：US13436337
申请日：2012-03-30
申请人： Anil Vasudevan , Glenn J. Hinton , Yadong Li
发明人： Anil Vasudevan , Glenn J. Hinton , Yadong Li
IPC分类号： G06F3/00 , G06F12/08 , H04L12/861 , G06F5/10
CPC分类号： G06F12/084 , G06F5/10 , H04L49/90
摘要： Examples are disclosed for establishing a window for a queue structure maintained in a cache for a processing element for a network device. The processing element may be configured to operate in cooperation with an input/output device such as a network interface card. In some of these examples, the window may include portions of the queue structure having identifiers to active allocated buffers maintained in memory for the network device. The active allocated buffers may be configured to maintain or store data received or to be forwarded by the input/output device. For these examples, the window may be adjusted based on information gathered while the identifiers are read from or written to the portions of the queue structure.
摘要翻译：公开了用于建立用于网络设备的处理元件的高速缓存中维护的队列结构的窗口的示例。处理元件可以被配置为与诸如网络接口卡的输入/输出设备协作操作。在这些示例中的一些示例中，窗口可以包括具有对于网络设备的存储器中维护的主动分配缓冲区的标识符的队列结构的部分。活动分配的缓冲器可以被配置为维护或存储由输入/输出设备接收或要转发的数据。对于这些示例，可以基于从标识符从队列结构的部分读取或写入标识符时收集的信息来调整窗口。

90. 发明授权

US09081688B2 Obtaining data for redundant multithreading (RMT) execution 有权
标题翻译：获取冗余多线程（RMT）执行的数据
公开(公告)号：US09081688B2
公开(公告)日：2015-07-14
申请号：US12317801
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/0817
摘要： In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于向第一高速缓存提供处于独占状态的高速缓存块的方法，并且当访问两个高速缓存的核心正在执行冗余线程时，以独占状态将相同的高速缓存块提供给第二高速缓存。描述和要求保护其他实施例。

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