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81. 发明申请

US20160179545A1 INSTRUCTION AND LOGIC FOR REGISTER BASED HARDWARE MEMORY RENAMING 审中-公开
标题翻译：基于注册的硬件存储器恢复的指令和逻辑
公开(公告)号：US20160179545A1
公开(公告)日：2016-06-23
申请号：US14581268
申请日：2014-12-23
申请人： Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
发明人： Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/30043 , G06F9/30101 , G06F9/30116 , G06F9/3802 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/3891
摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.
摘要翻译：处理器包括核心，存储器子系统，预测器模块和存储器重命名模块。预测器模块可以包括用于识别存储指令和加载指令之间的依赖性的第一逻辑，以及基于所识别的依赖关系将存储器重命名（MRN）寄存器分配给存储指令和加载指令的第二逻辑。此外，存储器重命名模块可以包括第三逻辑，用于基于所分配的MRN寄存器将与存储指令相关联的第一逻辑寄存器中的信息直接复制到与加载指令相关联的第二逻辑寄存器。

82. 发明授权

US09229524B2 Performing local power gating in a processor 有权
标题翻译：在处理器中执行本地电源门控
公开(公告)号：US09229524B2
公开(公告)日：2016-01-05
申请号：US13534601
申请日：2012-06-27
申请人： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
发明人： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
IPC分类号： G06F1/32 , G06F9/30 , G06F9/38
CPC分类号： G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
摘要： In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括执行单元，用于执行第一类型的指令，耦合到执行单元的本地电源门电路，以在第二执行单元执行第二类型的指令时对所述执行单元进行电源门控，以及控制器，其耦合到所述本地电源门电路，以使得当指令流不包括所述第一类型的指令时，所述控制器对所述执行单元进行供电。描述和要求保护其他实施例。

83. 发明申请

US20150261590A1 CONDITIONAL MEMORY FAULT ASSIST SUPPRESSION 有权
标题翻译：条件记忆障碍协助抑制
公开(公告)号：US20150261590A1
公开(公告)日：2015-09-17
申请号：US14214910
申请日：2014-03-15
申请人： Zeev Sperber , Robert Valentine , Offer Levy , Michael Mishaeli , Gal Ofir
发明人： Zeev Sperber , Robert Valentine , Offer Levy , Michael Mishaeli , Gal Ofir
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/0721 , G06F11/073
摘要： In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.
摘要翻译：在一些公开的实施例中，指令执行逻辑提供条件存储器故障辅助抑制。处理器的一些实施例包括解码级，以对一个或多个指令进行解码，该指令指定：一组存储器操作，一个或多个寄存器和一个或多个存储器地址。响应于一个或多个解码指令的一个或多个执行单元为该组存储器操作生成所述一个或多个存储器地址。指令执行逻辑记录一个或多个故障抑制位以指示该组存储器操作中的一个或多个部分被屏蔽。当所述一组存储器操作中的所述故障之一对应于由所述一组存储器操作屏蔽的所述一组存储器操作的一部分时，故障产生逻辑被抑制为考虑与所述一组存储器操作中的故障的一个存储器操作相对应的存储器故障，更多的故障抑制位。

84. 发明申请

US20140208080A1 APPARATUS AND METHOD FOR DOWN CONVERSION OF DATA TYPES 审中-公开
标题翻译：数据类型下变换的装置和方法
公开(公告)号：US20140208080A1
公开(公告)日：2014-07-24
申请号：US13997006
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30036
摘要： An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit(s) indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.
摘要翻译：描述了用于从源操作数到具有掩蔽的目的地操作数的下变频的装置和方法。例如，根据一个实施例的方法包括以下操作：将从第一值下变频的源操作数值读取到下变换值并存储在目的位置; 读取存储在掩码寄存器中的每个掩码寄存器位，指示是否对源操作数值执行掩蔽操作或转换操作的掩码寄存器位; 如果屏蔽寄存器位指示要执行屏蔽操作，则执行指定的屏蔽操作并将掩蔽操作的结果存储在目的地位置中; 并且如果屏蔽寄存器位指示不执行屏蔽操作，则对源操作数值进行下变频并将下变频值存储在指定的目的地位置。

85. 发明申请

US20140059322A1 APPARATUS AND METHOD FOR BROADCASTING FROM A GENERAL PURPOSE REGISTER TO A VECTOR REGISTER 审中-公开
标题翻译：从通用寄存器向矢量寄存器广播的装置和方法
公开(公告)号：US20140059322A1
公开(公告)日：2014-02-27
申请号：US13996800
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L Toll , Mark J Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L Toll , Mark J Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F15/80
摘要： An apparatus and method are described for broadcasting from a general purpose source register to a destination vector register. For example, a method according to one embodiment includes the following operations: selecting data element position N within the destination vector register to be updated; broadcasting a set of data from the general purpose source register to data element position N within the destination vector register if a mask indicator is set to a first indication; and either copying zeroes to data element position N within the destination vector register or maintaining existing values stored within data element position N within the destination vector register if the mask indicator is set to a second indication.
摘要翻译：描述了用于从通用源寄存器到目的地向量寄存器的广播的装置和方法。例如，根据一个实施例的方法包括以下操作：选择要更新的目的地向量寄存器内的数据元素位置N; 如果将掩码指示符设置为第一指示，则将一组数据从通用源寄存器传送到目的地向量寄存器内的数据元素位置N; 并且如果掩模指示符被设置为第二指示，则将零值复制到目的地向量寄存器内的数据元素位置N，或者保持存储在目的地向量寄存器内的数据元素位置N内的现有值。

86. 发明申请

US20130326160A1 GATHER USING INDEX ARRAY AND FINITE STATE MACHINE 有权
标题翻译：使用索引阵列和有限状态机
公开(公告)号：US20130326160A1
公开(公告)日：2013-12-05
申请号：US13487184
申请日：2012-06-02
申请人： Zeev Sperber , Robert Valentine , Guv Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
发明人： Zeev Sperber , Robert Valentine , Guv Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
IPC分类号： G06F12/00
CPC分类号： G06F15/8007 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3887
摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
摘要翻译：公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。设备的实施例可以包括：解码逻辑以解码分散/收集指令并生成一组微操作，以及索引阵列以保存一组索引和相应的一组掩码元素。有限状态机有助于收集操作。地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。如果mask元素具有第一个值，则访问地址以加载相应的数据元素。根据相应的注册位置的索引，将数据元素写入到目的地向量寄存器的寄存器位置。响应于其相应负载的完成，对应的屏蔽元件的值从第一值改变为第二值。

87. 发明申请

US20130275727A1 Processors, Methods, Systems, and Instructions to Generate Sequences of Integers in which Integers in Consecutive Positions Differ by a Constant Integer Stride and Where a Smallest Integer is Offset from Zero by an Integer Offset 有权
标题翻译：处理器，方法，系统和生成整数序列的指令，其中连续位置中的整数不同于整数步长，最小整数由零整数偏移量偏移
公开(公告)号：US20130275727A1
公开(公告)日：2013-10-17
申请号：US13976580
申请日：2011-12-22
申请人： Seth Abraham , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Zeev Sperber , Amit Gradstein
发明人： Seth Abraham , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：方面的方法包括接收指令。该指令指示整数步长，表示整数偏移，并指示目的地存储位置。结果存储在目的地存储位置以响应该指令。结果包括以数字顺序的至少四个整数的序列，其中至少四个整数中的最小的整数与零与整数偏移不同，并且具有与整数步长不同的连续位置中的序列的所有整数。公开了其它方法，装置，系统和指令。

88. 发明申请

US20120084533A1 Efficient Parallel Floating Point Exception Handling In A Processor 审中-公开
标题翻译：处理器中有效的并行浮点异常处理
公开(公告)号：US20120084533A1
公开(公告)日：2012-04-05
申请号：US13325559
申请日：2011-12-14
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/30 , G06F9/38 , G06F9/302
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

89. 发明申请

US20110208918A1 MOVE ELIMINATION AND NEXT PAGE PREFETCHER 有权
标题翻译：移动消除和下一页预选
公开(公告)号：US20110208918A1
公开(公告)日：2011-08-25
申请号：US12978513
申请日：2010-12-24
申请人： Shlomo Raikin , David J. Sager , Zeev Sperber , Evgeni Krimer , Ori Lempel , Stanislav Shwartsman , Adi Yoaz , Omer Golz
发明人： Shlomo Raikin , David J. Sager , Zeev Sperber , Evgeni Krimer , Ori Lempel , Stanislav Shwartsman , Adi Yoaz , Omer Golz
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/30032 , G06F9/3824 , G06F9/384 , Y02D10/13
摘要： Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.
摘要翻译：描述与硬件移动消除和/或下一页预取相关的方法和装置。在一些实施例中，逻辑可以基于存储的数据提供硬件移动消除。在一个实施例中，公开了下一页预取器。还描述和要求保护其他实施例。

90. 发明申请

US20090328057A1 SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX 有权
标题翻译：用于预留站负载依赖矩阵的系统和方法
公开(公告)号：US20090328057A1
公开(公告)日：2009-12-31
申请号：US12164666
申请日：2008-06-30
申请人： Sagi LAHAV , Guy Patkin , Zeev Sperber , Herbert Hum , Shih-Lien Lu , Srikanth T. Srinivasan
发明人： Sagi LAHAV , Guy Patkin , Zeev Sperber , Herbert Hum , Shih-Lien Lu , Srikanth T. Srinivasan
IPC分类号： G06F9/445
CPC分类号： G06F9/3838 , G06F9/3017 , G06F9/3834 , G06F9/384 , G06F9/3859
摘要： A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.
摘要翻译：设备和方法可以获取用于执行的指令或微操作。可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。可以存储对应于第一指令所依赖的每个源值的值。可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。可以在与指令相关联的存储值表示满足依赖性之后执行指令。

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