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81. 发明授权

US08595463B2 Memory architecture with policy based data storage 失效
标题翻译：内存架构与基于策略的数据存储
公开(公告)号：US08595463B2
公开(公告)日：2013-11-26
申请号：US12882551
申请日：2010-09-15
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/06 , G06F12/10 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved.
摘要翻译：介绍了一种用于存储器管理的计算系统和方法。存储器或I / O控制器接收写入请求，其中写入的数据2与地址相关联。提示信息可以与地址相关联，并且可以涉及诸如历史，O / S方向，数据优先级，作业优先级，作业重要性，作业类别，存储器类型，I / O发送者ID，延迟，功率，写入成本或读取成本组件。存储器控制器可以询问提示信息以确定存储关联数据的位置（例如，什么存储器类型或类别）。因此，数据被有效地存储在系统内。提示信息也可以用于跟踪写入后信息，并且可以被询问以确定是否应该发生数据迁移，并且应该向哪个新的存储器类型或类别移动数据。

82. 发明授权

US08495318B2 Memory page management in a tiered memory system 有权
标题翻译：分层内存系统中的内存页面管理
公开(公告)号：US08495318B2
公开(公告)日：2013-07-23
申请号：US12843718
申请日：2010-07-26
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1009 , G06F11/3471 , G06F12/1475 , G06F2201/88
摘要： Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.
摘要翻译：包括包括至少一个用于存储多个条目的页表的系统的系统中的存储器页面管理，每个条目与存储器页面相关联，每个条目包括页面的地址和页面的存储器层。该系统还包括配置用于将与条目相关联的页面分配给软件模块的控制程序，来自至少两个不同存储器层的所分配的页面。该系统还包括能够独立于控制程序操作的控制程序的代理，被配置为接收对所分配的页面的授权密钥的代理，以及响应于授权密钥在不同存储器层之间迁移分配的页面。

83. 发明申请

US20130181738A1 SOFT ERROR RESILIENT FPGA 失效
公开(公告)号：US20130181738A1
公开(公告)日：2013-07-18
申请号：US13352900
申请日：2012-01-18
申请人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
发明人： Luiz C. Alves , William J. Clarke , K. Paul Muller , Robert B. Tremaine
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/17764
摘要： A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

84. 发明申请

US20130038380A1 IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK 有权
标题翻译：在TSV堆栈中进行芯片校准
公开(公告)号：US20130038380A1
公开(公告)日：2013-02-14
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： H03H11/00 , G06F17/50 , H01L29/68
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

85. 发明授权

US08212588B2 Opportunistic bus access latency 失效
标题翻译：机会总线访问延迟
公开(公告)号：US08212588B2
公开(公告)日：2012-07-03
申请号：US12729455
申请日：2010-03-23
申请人： Theodore P. Haggis , Robert B. Likovich, Jr. , James A. Mossman , Tiffany Tamaddoni-Jahromi , Robert B. Tremaine
发明人： Theodore P. Haggis , Robert B. Likovich, Jr. , James A. Mossman , Tiffany Tamaddoni-Jahromi , Robert B. Tremaine
IPC分类号： H03K19/094
CPC分类号： G06F13/4243
摘要： A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.
摘要翻译：一种总线系统，其包括耦合到公共信号总线的多个信号驱动装置，耦合到公共信号总线的总线控制电路和比较电路。多个信号驱动装置包括第一信号驱动装置和第二信号驱动装置。总线控制器包括具有用于每个信号驱动装置的可配置延迟的延迟补偿电路。延迟补偿电路具有与第一信号驱动装置相关联的电流延迟链配置。比较电路被配置为将与第一信号驱动装置相关联的第一可配置延迟与与多个信号驱动装置中的第二信号驱动装置相关联的第二可配置延迟进行比较，并且用于响应于比较来产生响应于指示是否当前延迟链配置可以由第二信号驱动装置使用。

86. 发明申请

US20110126200A1 Scheduling for functional units on simultaneous multi-threaded processors 失效
标题翻译：在同时多线程处理器上调度功能单元
公开(公告)号：US20110126200A1
公开(公告)日：2011-05-26
申请号：US11488970
申请日：2006-07-19
申请人： Orran Y. Krieger , Bryan S. Rosenburg , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Bryan S. Rosenburg , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F9/46
CPC分类号： G06F9/5033
摘要： A method and system for scheduling threads on simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system determines thread scheduling based on the information.
摘要翻译：公开了一种用于在同时多线程处理器上调度线程的方法和系统。硬件和操作系统彼此通信，提供与处理元件上执行的线程的线程属性相关的信息。操作系统根据信息确定线程调度。

87. 发明授权

US07539842B2 Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables 失效
标题翻译：计算机存储器系统，用于根据存储在虚拟地址转换表中的物理存储器组织信息来选择存储器总线
公开(公告)号：US07539842B2
公开(公告)日：2009-05-26
申请号：US11464503
申请日：2006-08-15
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/10
CPC分类号： G06F12/0607 , G06F12/10 , G06F13/28
摘要： Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.
摘要翻译：用于程序定向存储器访问模式的系统和方法，包括具有存储器的存储器系统，存储器控制器和虚拟存储器管理系统。存储器包括被组织成一个或多个物理组的多个存储器件，可通过相关联的总线访问以传送数据和控制信息。存储器控制器接收并响应包含应用访问信息的存储器访问请求，以控制存储器内的访问模式和数据组织。响应于存储器访问请求包括访问一个或多个存储器设备。虚拟存储器管理系统包括：多个页表条目，用于将虚拟存储器地址映射到存储器中的实际地址; 响应于应用程序访问信息的指示状态，用于指示相关联的页面的实际存储器如何被物理地组织在存储器内; 以及用于将提示状态传送到存储器控制器的装置。

88. 发明申请

US20080263278A1 CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT 有权
标题翻译：基于运行时性能数据或软件提示的缓存重新配置
公开(公告)号：US20080263278A1
公开(公告)日：2008-10-23
申请号：US12130752
申请日：2008-05-30
申请人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译：提供了一种重新配置高速缓冲存储器的方法。一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

89. 发明申请

US20080022283A1 Quality of service scheduling for simultaneous multi-threaded processors 审中-公开
标题翻译：同步多线程处理器的服务质量调度
公开(公告)号：US20080022283A1
公开(公告)日：2008-01-24
申请号：US11488977
申请日：2006-07-19
申请人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/3851 , G06F2209/5018 , G06F2209/5019 , G06F2209/508
摘要： A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.
摘要翻译：公开了一种用于提供同时多线程处理器的服务质量保证的方法和系统。硬件和操作系统彼此通信，提供与处理元件上执行的线程的线程属性相关的信息。操作系统至少部分地基于传达的信息来控制线程的调度，并提供服务质量保证。

90. 发明申请

US20080022076A1 Operating system thread scheduling for optimal heat dissipation 失效
标题翻译：操作系统线程调度，实现最佳散热
公开(公告)号：US20080022076A1
公开(公告)日：2008-01-24
申请号：US11482270
申请日：2006-07-07
申请人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F15/00
CPC分类号： G06F9/5033 , G06F1/206 , G06F9/5094 , G06F2209/5013 , G06F2209/5018 , G06F2209/508 , Y02D10/22
摘要： A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.
摘要翻译：提供了一种用于最佳散热的线程调度的方法和系统。温度传感器测量处理器芯片各个部分的温度。检测到的温度被报告给操作系统等用于调度线程。在一个方面，观察到的温度值记录在寄存器上。操作系统等读取寄存器并基于温度值调度线程。

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