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81. 发明申请

US20070218665A1 Cross-point memory array 审中-公开
标题翻译：交叉点存储器阵列
公开(公告)号：US20070218665A1
公开(公告)日：2007-09-20
申请号：US11637967
申请日：2006-12-13
申请人： Pantas Sutardja , Albert Wu
发明人： Pantas Sutardja , Albert Wu
IPC分类号： H01L21/28
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141
摘要： A phase-change memory (PCM) system comprises a PCM cell array that comprises a plurality of PCM cells. Each of the PCM cells includes diode arranged adjacent to a metallization layer; a heater element arranged adjacent to the diode, and a phase-change material arranged adjacent to the heater element.
摘要翻译：相变存储器（PCM）系统包括包括多个PCM单元的PCM单元阵列。每个PCM单元包括邻近金属化层布置的二极管; 与二极管相邻布置的加热器元件，以及邻近加热器元件设置的相变材料。

82. 发明授权

US07269778B1 Data coding for enforcing constraints on ones and zeros in a communications channel 有权
标题翻译：数据编码，用于在通信信道中对1和0执行约束
公开(公告)号：US07269778B1
公开(公告)日：2007-09-11
申请号：US10423552
申请日：2003-04-25
申请人： Weishi Feng , Pantas Sutardja
发明人： Weishi Feng , Pantas Sutardja
IPC分类号： H03M13/00
CPC分类号： H03M5/145
摘要： A communications channel such as a data storage system removes unwanted bit patterns from user data without using run length limited coding on the user data. A buffer receives the user data. A data dependent scrambler communicates with the buffer and selects one of a plurality of scrambling sequences based the user data stored in the buffer or generates a scrambling sequence based on the user data stored in the buffer. A scrambling device communicates with the data dependent scrambler and scrambles the user data stored in the buffer with the selected scrambling sequence from the data dependent scrambler.
摘要翻译：诸如数据存储系统的通信信道从用户数据中去除不想要的比特模式，而不对用户数据使用游程长度限制编码。缓冲区接收用户数据。数据相关扰频器与缓冲器通信，并且基于存储在缓冲器中的用户数据选择多个加扰序列中的一个，或者基于存储在缓冲器中的用户数据产生加扰序列。加扰设备与数据相关的加扰器进行通信，并且从存储在数据的扰频器中选择的加扰序列加扰存储在缓冲器中的用户数据。

83. 发明申请

US20070171730A1 Method and system for error correction in flash memory 有权
标题翻译：闪存中纠错方法和系统
公开(公告)号：US20070171730A1
公开(公告)日：2007-07-26
申请号：US11598117
申请日：2006-11-08
申请人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
发明人： Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
IPC分类号： G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储器单元包括适于存储由第一数字级别表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

84. 发明申请

US20070171714A1 Flash memory with coding and signal processing 有权
标题翻译：闪存与编码和信号处理
公开(公告)号：US20070171714A1
公开(公告)日：2007-07-26
申请号：US11598178
申请日：2006-11-08
申请人： Zining Wu , Pantas Sutardja
发明人： Zining Wu , Pantas Sutardja
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C29/00 , G11C2029/0411 , G11C2211/5641
摘要： A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.
摘要翻译：固态非易失性存储器单元部分地包括编码器，适用于存储由编码器编码的数据的多级固态非易失性存储器阵列，以及适于对从存储器阵列检索的数据进行解码的解码器。存储器阵列可以是闪存EEPROM阵列。存储器单元可选地包括调制器和解调器。由调制器调制的数据被存储在存储器阵列中。解调器解调从存储器阵列检索的调制数据。

85. 发明申请

US20070070845A1 Automatic write strategy calibration method for optical drive 失效
标题翻译：光驱自动写策略校准方法
公开(公告)号：US20070070845A1
公开(公告)日：2007-03-29
申请号：US11337332
申请日：2006-01-23
申请人： Pantas Sutardja
发明人： Pantas Sutardja
IPC分类号： G11B7/12
CPC分类号： G11B7/00456 , G11B7/0045 , G11B7/1267 , G11B2007/0006
摘要： A write strategy calibration system for an optical media playback device comprises memory for storing a write strategy table. A control module generates a write signal to write a training pattern to an optical storage medium according to calibration data stored in the write strategy table. A write strategy analysis module receives a read signal indicative of the training pattern written to the optical storage medium and adjusts the calibration data according to the read signal.
摘要翻译：用于光学媒体回放设备的写入策略校准系统包括用于存储写入策略表的存储器。控制模块根据存储在写入策略表中的校准数据生成写信号以将训练模式写入光存储介质。写策略分析模块接收指示写入光存储介质的训练模式的读信号，并根据读信号调整校准数据。

86. 发明授权

US07184231B1 Precompensation circuit for magnetic recording 有权
标题翻译：磁记录预补偿电路
公开(公告)号：US07184231B1
公开(公告)日：2007-02-27
申请号：US11250373
申请日：2005-10-17
申请人： Pantas Sutardja , Chi Fung Cheng
发明人： Pantas Sutardja , Chi Fung Cheng
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B5/09 , H03L7/06
摘要： In a precompensation circuit for magnetic recording of data signals, a clock produces clock signals at a predetermined rate to clock the recording of the data signals. A clock delay generator generates clock delay data relative to the generated clock signals for successive data signals to be recorded. The clock delay data for each data signal is formed according to the states of a set of adjacent data signals. n>1 programmable clock delay units operate sequentially to control the recording times of the successive data signals. Each clock delay unit receives the clock delay data for one data signal in each sequence of n successive data signals and determines recording time of the one data signal according to the clock delay data for the one data signal in the sequence.
摘要翻译：在用于数据信号的磁记录的预补偿电路中，时钟以预定速率产生时钟信号以对数据信号的记录进行时钟。时钟延迟发生器相对于所记录的连续数据信号产生的时钟信号产生时钟延迟数据。根据一组相邻数据信号的状态，形成每个数据信号的时钟延迟数据。 n> 1个可编程时钟延迟单元依次操作以控制连续数据信号的记录时间。每个时钟延迟单元在n个连续数据信号的每个序列中接收一个数据信号的时钟延迟数据，并根据序列中的一个数据信号的时钟延迟数据确定一个数据信号的记录时间。

87. 发明授权

US07167331B1 Electrostatic discharge protection circuit for magneto-resistive read elements 有权
标题翻译：用于磁阻读取元件的静电放电保护电路
公开(公告)号：US07167331B1
公开(公告)日：2007-01-23
申请号：US10877033
申请日：2004-06-25
申请人： Pantas Sutardja
发明人： Pantas Sutardja
IPC分类号： G11B5/02 , G11B5/127 , G11B5/09
CPC分类号： G11B5/40
摘要： A magnetic storage system includes a read element including a tunneling giant magneto-resistive (TGMR) sensor. A shunting device includes a control terminal and first and second terminals that communicate with respective first and second terminals of the read element. The shunting device shorts said first and second terminals when said control terminal is not powered to protect the read element from electrostatic discharge. A first voltage limiting circuit limits voltage that is input to first terminals of said shunting device and said read element. Said first voltage limiting circuit includes first and second diodes. An anode of said first diode and a cathode of said second diode communicate with said first terminal of said read element and said first terminal of said shunting device and a cathode of said first diode and an anode of said second diode communicate.
摘要翻译：一种磁存储系统包括一个包含隧道式巨磁阻（TGMR）传感器的读取元件。分流装置包括控制端子和与读取元件的相应第一和第二端子通信的第一和第二端子。当所述控制端子未通电时，分流装置将所述第一和第二端子短路以保护所述读取元件免受静电放电。第一限压电路限制输入到所述分流装置和所述读取元件的第一端子的电压。所述第一限压电路包括第一和第二二极管。所述第一二极管的阳极和所述第二二极管的阴极与所述读取元件的所述第一端子和所述分流装置的所述第一端子连通，并且所述第一二极管的阴极和所述第二二极管的阳极连通。

88. 发明授权

US07158333B1 Up-sampled filtering for servo demodulation 有权
标题翻译：用于伺服解调的上采样滤波
公开(公告)号：US07158333B1
公开(公告)日：2007-01-02
申请号：US10682138
申请日：2003-10-09
申请人： Pantas Sutardja , Michael Madden
发明人： Pantas Sutardja , Michael Madden
IPC分类号： G11B5/596 , G11B5/09
CPC分类号： G11B5/59622 , G11B5/556
摘要： An apparatus, method, and system for providing a fine adjustment for transducing head positioning in a hard disk drive (HDD). The apparatus, method, and system include reading a positioning error field wherein the resulting signal is a substantially sinusoidal position error signal (PES), filtering the PES to remove low frequencies and attenuate high frequencies, sample the filtered PES at a multiple of the channel frequency, filter the higher frequency harmonics, down sample the PES, and provide a signal proportional to the amplitude of the down sampled PES. This signal is the reference signal to the head positioning servo.
摘要翻译：一种用于提供用于在硬盘驱动器（HDD）中转换头部定位的微调的装置，方法和系统。装置，方法和系统包括读取定位误差场，其中所得到的信号是基本上正弦的位置误差信号（PES），对PES进行滤波以去除低频并衰减高频，以频率倍数采样经滤波的PES 频率，滤波较高频率的谐波，向下采样PES，并提供与下采样PES幅度成比例的信号。该信号是头定位伺服的参考信号。

89. 发明授权

US06594098B1 Acquistion timing loop for read channel 有权
标题翻译：读取通道的采集定时循环
公开(公告)号：US06594098B1
公开(公告)日：2003-07-15
申请号：US09660392
申请日：2000-09-12
申请人： Pantas Sutardja
发明人： Pantas Sutardja
IPC分类号： G11B509
CPC分类号： G11B20/10027 , G11B5/012 , G11B5/09 , G11B20/10009 , G11B20/1403
摘要： A signal from a storage medium is processed in a data channel to form digital data. An amplifier and a sampler convert the storage medium signal into a timed sample sequence. A first equalizer and adjuster operates to equalize the timed sample sequence and to adjust the gain of the amplifier and timing of the sampler in a preamble segment of the signal. A second equalizer and adjuster circuit to equalize the timed sample sequence for detection and to adjust the gain of the amplifier and the timing of the sampler operates in a user data segment of the signal. An FIR equalizing filter in the second equalizer and adjuster circuit is controlled by a set of parameters to accurately equalize a large range of waveforms in the user data segment of the signal and an FIR equalizing filter in the first equalizer and adjuster circuit is controlled by a smaller set of related set of parameters adapted to accommodate rapid adjustment during synchronization in the preamble segment of the signal.
摘要翻译：来自存储介质的信号在数据信道中被处理以形成数字数据。放大器和采样器将存储介质信号转换为定时采样序列。第一均衡器和调节器用于均衡定时采样序列，并调整放大器的增益和信号前导码段中的采样器的定时。用于均衡用于检测的定时采样序列并调整放大器的增益并且采样器的定时的第二均衡器和调节器电路在信号的用户数据段中操作。第二均衡器和调节器电路中的FIR均衡滤波器由一组参数控制，以精确地均衡信号的用户数据段中的大范围波形和第一均衡器中的FIR均衡滤波器，并且调节器电路由较小的相关参数集合适于在信号的前导码段中的同步期间适应快速调整。

90. 发明授权

US6125154A Digital servo channel for recording apparatus 失效
公开(公告)号：US6125154A
公开(公告)日：2000-09-26
申请号：US49830
申请日：1998-03-27
申请人： Pantas Sutardja
发明人： Pantas Sutardja
IPC分类号： G11B20/14 , H04L7/04 , H04L27/08
CPC分类号： G11B20/14 , H04L7/04
摘要： A servo channel digitally processes the data read from a magnetic media. The channel uses both edges of a system clock to detect peaks and generates position error systems by an area-based automatic gear control loop. By altering the sample delay, the channel digitally, up-samples at higher rates without requiring a higher system clock.

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