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    • 86. 发明授权
    • Semiconductor component and method of manufacture
    • 半导体元件及制造方法
    • US06933620B2
    • 2005-08-23
    • US10915638
    • 2004-08-09
    • Scott LunningKarsten WieczorekThorsten Kammler
    • Scott LunningKarsten WieczorekThorsten Kammler
    • H01L21/28H01L21/336H01L29/423H01L29/78H01L27/088
    • H01L29/6659H01L21/28114H01L29/42376H01L29/665H01L29/6656H01L29/7833Y10S257/90
    • An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).
    • 一种具有降低的栅极电阻的绝缘栅极半导体器件(100)和用于制造半导体器件(100)的方法。 栅极结构(112)形成在半导体衬底(102)的主表面(104)上。 在栅极结构(112)的侧壁附近形成连续的氮化物间隔物(118,128)。 氮化物间隔物(118,128)使用单个蚀刻被蚀刻和凹陷以暴露栅极结构(112)的上部(115A,117A)。 源极(132)和漏极(134)区域形成在半导体衬底(102)中。 硅化物区域(140,142,144)形成在栅极结构(112)和源极区域(132)和漏极区域(134)的顶表面(109)和暴露的上部(115A,117A) )。 电极(150,152,154)形成为与相应的栅极结构(112),源极区(132)和漏极区(134)的硅化物(140,142,144)接触。
    • 89. 发明授权
    • Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same
    • 在沟道区域具有逆向掺杂剂分布的半导体器件及其制造方法
    • US06881641B2
    • 2005-04-19
    • US10282980
    • 2002-10-29
    • Karsten WieczorekManfred HorstmannRolf Stephan
    • Karsten WieczorekManfred HorstmannRolf Stephan
    • H01L21/336H01L21/8238H01L29/10H01L21/331
    • H01L21/823807H01L29/1054H01L29/6659
    • An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
    • 在离子注入步骤之后在阱结构上提供外延生长的沟道层,并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要,沟道层可以是未掺杂的或稍微掺杂的,使得与常规器件相比,沟道层中最终获得的掺杂剂浓度显着降低,从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外,可以在阱结构和沟道层之间提供阻挡扩散层,以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度,扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。