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81. 发明授权

US6010960A Method and system for providing an interconnect having reduced failure rates due to voids 失效
标题翻译：用于提供由于空隙而具有降低的故障率的互连的方法和系统
公开(公告)号：US6010960A
公开(公告)日：2000-01-04
申请号：US959591
申请日：1997-10-29
申请人： Takeshi Nogami
发明人： Takeshi Nogami
IPC分类号： H01L21/768 , H01L21/28 , H01L21/283 , H01L21/44 , H01L21/441
CPC分类号： H01L21/76849 , H01L21/76847 , H01L21/76877
摘要： A system and method for providing an interconnect on a substrate is disclosed. The method and system include providing a first layer, a first barrier layer, and a second layer. The first layer is subject to electromigration and has a thickness. The thickness of the first layer is smaller than what is required to support formation of a void. The first barrier layer is resistant to electromigration. The first barrier layer is disposed between the first layer and the second layer. In a second aspect, the method and system include providing a first layer and a first barrier layer. The first layer is subject to electromigration and has a thickness. The thickness of the first layer is smaller than what is required to support formation of a void. The first barrier layer is resistant to electromigration.
摘要翻译：公开了一种用于在衬底上提供互连的系统和方法。该方法和系统包括提供第一层，第一阻挡层和第二层。第一层经过电迁移并具有厚度。第一层的厚度小于支撑形成空隙所需的厚度。第一阻挡层耐电迁移。第一阻挡层设置在第一层和第二层之间。在第二方面，所述方法和系统包括提供第一层和第一阻挡层。第一层经过电迁移并具有厚度。第一层的厚度小于支撑形成空隙所需的厚度。第一阻挡层耐电迁移。

82. 发明授权

US5882498A Method for reducing oxidation of electroplating chamber contacts and improving uniform electroplating of a substrate 失效
标题翻译：降低电镀室触点氧化的方法，改善基板的均匀电镀
公开(公告)号：US5882498A
公开(公告)日：1999-03-16
申请号：US951805
申请日：1997-10-16
申请人： Valery Dubin , Takeshi Nogami
发明人： Valery Dubin , Takeshi Nogami
IPC分类号： C25D7/12 , C25D3/00 , C23C28/02 , C25D3/56
CPC分类号： C23C28/023 , C23C28/021 , C25D7/123
摘要： A method for electroplating a silicon substrate in manufacturing a semiconductive device is provided. Electroplating process chamber contacts or fingers used in positioning a silicon substrate or wafer during an electroplating process are plated with a metal layer to prevent oxidation of the contacts. Oxidation of the contacts may result in increased and varying resistance of the contacts and thus nonuniform plating of the silicon wafer and possibly even deplating of a seed layer. A 20 mA/cm.sup.2 current is applied to the contacts which are immersed in an electrolyte solution before loading a silicon wafer. A silicon wafer is then loaded into the electroplating process chamber containing the electrolyte solution. The preplating of the contacts enables the formation of a uniform metal layer on the silicon substrate. Additionally, voltage then may be applied to the contacts after unloading the silicon wafer to reduce oxidation. This electroplating method reduces expensive maintenance time in replacing or cleaning electroplating chamber contacts. The method also does not require expensive and complex electronics to monitor and supply current to the contacts.
摘要翻译：提供了一种用于在制造半导体器件中电镀硅衬底的方法。在电镀工艺期间用于定位硅衬底或晶片的电镀处理室触点或手指镀有金属层以防止触点的氧化。触点的氧化可导致触点的增加和变化的电阻，并因此导致硅晶片的不均匀电镀以及可能甚至脱落种子层。在加载硅晶片之前，将浸入电解质溶液的触点施加20mA / cm 2的电流。然后将硅晶片装入含有电解质溶液的电镀处理室中。触点的预镀是能够在硅衬底上形成均匀的金属层。此外，在卸载硅晶片之后，可以向触点施加电压以减少氧化。这种电镀方法可以减少更换或清洗电镀室触点的维护时间。该方法也不需要昂贵且复杂的电子元件来监视和提供电流到触点。

83. 发明授权

US5405792A Method of manufacturing schottky barrier gate type fet 失效
标题翻译：制造肖特基势垒栅型的方法
公开(公告)号：US5405792A
公开(公告)日：1995-04-11
申请号：US941151
申请日：1992-09-04
申请人： Takeshi Nogami , Hiroshi Iwasaki
发明人： Takeshi Nogami , Hiroshi Iwasaki
IPC分类号： H01L21/266 , H01L21/338 , H01L21/306 , H01L21/44
CPC分类号： H01L29/66878 , H01L21/266 , Y10S148/14
摘要： The method of manufacturing the SB FET according to the present invention includes a first step of forming a refractory metal film on a semiconductor substrate, a second step of forming a first ion-implanted region within the semiconductor substrate, by an ion implantation process, a third step, independent of the second step, of forming second and third ion implantation regions in the semiconductor substrate by an ion implantation process during which impurity ions pass through the first film, with the second and third ion implantation regions being adjacent to the first ion implanted region. A fourth step of forming a channel region, source region and drain region by annealing to activate said first, second, and third ion implanted regions using the first film as a protective film, and bringing the first film in Schottky contact with the channel region, a fifth step of forming a Schottky gate electrode in Schottky contact with the channel region by patterning the first film after the channel, source and drain regions have been formed, with the first film being selectively maintained to prevent exposure of the channel region underlying the Schottky gate electrode, and a sixth step of forming a second film made of a refractory metal or a refractory metal compound on the first film forming a portion of said Schottky gate electrode.
摘要翻译：根据本发明的制造SB FET的方法包括在半导体衬底上形成难熔金属膜的第一步骤，通过离子注入工艺在半导体衬底内形成第一离子注入区域的第二步骤，第三步，独立于第二步骤，通过离子注入工艺在半导体衬底中形成第二和第三离子注入区，在该过程中，杂质离子通过第一膜，第二和第三离子注入区与第一离子相邻植入区域。通过退火形成沟道区域，源极区域和漏极区域的第四步骤，以使用第一膜膜作为保护膜来激活所述第一，第二和第三离子注入区域，并使第一膜片与沟道区域肖特基接触，通过在沟道，源极和漏极区域形成之后对第一膜进行构图而形成肖特基接触的肖特基栅电极的第五步骤，其中第一膜被选择性地保持以防止肖特基下方的沟道区域的暴露栅电极，以及在形成所述肖特基栅电极的一部分的第一膜上形成由难熔金属或难熔金属化合物制成的第二膜的第六步骤。

84. 发明授权

US5187111A Method of manufacturing Schottky barrier gate FET 失效
标题翻译：制造肖特基势垒栅极的方法
公开(公告)号：US5187111A
公开(公告)日：1993-02-16
申请号：US688711
申请日：1991-04-23
申请人： Takeshi Nogami , Hiroshi Iwasaki
发明人： Takeshi Nogami , Hiroshi Iwasaki
IPC分类号： H01L21/266 , H01L21/338
CPC分类号： H01L29/66878 , H01L21/266 , Y10S148/14
摘要： The method of manufacturing the SB FET according to the present invention includes a first step of forming a first WN metal film on a GaAs substrate, a second step of forming a first ion-implanted region within the GaAs substrate, by ion implantation of n-type impurities, a third step of forming a second Mo metal film, a fourth step of forming second and third ion-implanted regions adjacent to said first ion-implanted region, within the GaAs substrate, and a fifth step of activating said first, second, and third ion-implanted regions. In the ion implantation of the second step, impurity ions are implanted into the GaAs substrate, through the first metal film. In the fifth step, the first metal film serves as a protective film during the activation of the first, second, and third ion-implanted regions.
摘要翻译：根据本发明的制造SB FET的方法包括在GaAs衬底上形成第一WN金属膜的第一步骤，通过n型离子注入形成GaAs衬底内的第一离子注入区域的第二步骤，形成第二Mo金属膜的第三步骤，在GaAs衬底内形成与所述第一离子注入区域相邻的第二和第三离子注入区域的第四步骤，以及第五步骤，激活所述第一，第二，和第三离子注入区域。在第二步的离子注入中，通过第一金属膜将杂质离子注入到GaAs衬底中。在第五步骤中，第一金属膜在第一，第二和第三离子注入区域的激活期间用作保护膜。

85. 发明授权

US09379057B2 Method and structure to reduce the electric field in semiconductor wiring interconnects 有权
标题翻译：降低半导体布线互连电场的方法和结构
公开(公告)号：US09379057B2
公开(公告)日：2016-06-28
申请号：US14474935
申请日：2014-09-02
申请人： Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
发明人： Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/528 , H01L21/76804 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76883 , H01L23/5226 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.
摘要翻译：本发明的实施例提供了在后端（BEOL）结构中的通孔和相邻金属线之间的距离增加。铜合金种子层沉积在形成在电介质层中的沟槽中。然后用铜填充沟槽。然后，在退火期间，当锰在介电层中被拉出时，进行退火以形成使用诸如锰的种子层成分的自形成势垒。自形成障碍物设置在电介质层的肩部区域上，增加了通孔及其相邻金属线之间的有效距离。

86. 发明申请

US20160064321A1 METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS 有权
公开(公告)号：US20160064321A1
公开(公告)日：2016-03-03
申请号：US14474935
申请日：2014-09-02
申请人： Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
发明人： Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
IPC分类号： H01L23/528 , H01L23/522 , H01L23/532 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76804 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76883 , H01L23/5226 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.

87. 发明授权

US08658533B2 Semiconductor interconnect structure with multi-layered seed layer providing enhanced reliability and minimizing electromigration 失效
标题翻译：具有多层种子层的半导体互连结构提供增强的可靠性和最小化电迁移
公开(公告)号：US08658533B2
公开(公告)日：2014-02-25
申请号：US13044660
申请日：2011-03-10
申请人： Daniel C Edelstein , Takeshi Nogami
发明人： Daniel C Edelstein , Takeshi Nogami
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/44
CPC分类号： C23C16/45523 , C23C16/14 , C23C16/18 , C23C16/44 , H01L21/28556 , H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76883 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method for forming a multi-layered seed layer for semiconductor interconnections are disclosed. Specifically, the method and structure involves utilizing sequential catalytic chemical vapor deposition, which is followed by annealing, to form the multi-layered seed layer of an interconnect structure. The multi-layered seed layer will improve electromigration resistance, decrease void formation, and enhance reliability of ultra-large-scale integration (ULSI) chips.
摘要翻译：公开了用于形成用于半导体互连的多层种子层的互连结构和方法。具体地说，该方法和结构涉及利用顺序的催化化学气相沉积，随后进行退火以形成互连结构的多层种子层。多层种子层将提高超大规模集成（ULSI）芯片的电迁移阻力，减少空隙形成，提高可靠性。

88. 发明申请

US20130307150A1 COPPER INTERCONNECT STRUCTURE AND ITS FORMATION 有权
标题翻译：铜连接结构及其形成
公开(公告)号：US20130307150A1
公开(公告)日：2013-11-21
申请号：US13475526
申请日：2012-05-18
申请人： Daniel C. Edelstein , Takeshi Nogami , Christopher Parks , Tsong-Lin Tai
发明人： Daniel C. Edelstein , Takeshi Nogami , Christopher Parks , Tsong-Lin Tai
IPC分类号： H01L23/52 , H01L21/425
CPC分类号： H01L23/53238 , H01L21/76849 , H01L21/76867 , H01L21/76883 , H01L23/522 , H01L23/53209 , H01L23/5329 , H01L23/53295 , H01L24/76 , H01L24/82 , H01L2924/0002 , H01L2924/00
摘要： A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.
摘要翻译：具有改进的电迁移阻力的结构及其制造方法。具有改进的电迁移电阻的结构包括具有双层盖和介电覆盖层的体互连。双层帽包括底部金属部分和顶部金属氧化物部分。优选地，金属氧化物部分是MnO或MnSiO，金属部分是Mn或CuMn。通过用杂质（在优选实施例中为Mn）掺杂互连，然后在互连的顶部处产生晶格缺陷来产生该结构。这些缺陷驱使增加的杂质向互连顶表面迁移。当形成电介质盖层时，一部分与分离的杂质反应，从而在互连上形成双层盖。 Cu表面的晶格缺陷可以通过等离子体处理，离子注入，压缩薄膜或其他方式产生。

89. 发明授权

US08586468B2 Integrated circuit chip stack employing carbon nanotube interconnects 失效
标题翻译：采用碳纳米管互连的集成电路芯片堆叠
公开(公告)号：US08586468B2
公开(公告)日：2013-11-19
申请号：US11210586
申请日：2005-08-24
申请人： Takeshi Nogami , Masanaga Fukasawa
发明人： Takeshi Nogami , Masanaga Fukasawa
IPC分类号： H01L21/28
CPC分类号： H01L21/76898 , B82Y10/00 , H01L23/481 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： An arrangement of semiconductor chips is provided. The arrangement includes a plurality of stacked semiconductor chips each including an integrated circuit. At least one via is formed through the thickness of at least one of the semiconductor chips. A carbon nanotube conductor is formed in the via. The conductor has first and second opposite ends. The first end of the conductor is selectively interconnected with the integrated circuit of its semiconductor chip and the second end of the conductor is selectively interconnected with the integrated circuit of another of the semiconductor chips.
摘要翻译：提供了半导体芯片的布置。该装置包括多个堆叠的半导体芯片，每个堆叠的半导体芯片均包括集成电路。通过至少一个半导体芯片的厚度形成至少一个通孔。在通孔中形成碳纳米管导体。导体具有第一和第二相对端。导体的第一端与其半导体芯片的集成电路选择性地互连，并且导体的第二端选择性地与另一个半导体芯片的集成电路互连。

90. 发明授权

US08435887B2 Copper interconnect formation 失效
标题翻译：铜互连形成
公开(公告)号：US08435887B2
公开(公告)日：2013-05-07
申请号：US13151658
申请日：2011-06-02
申请人： James J. Kelly , Takeshi Nogami , Kazumichi Tsumura
发明人： James J. Kelly , Takeshi Nogami , Kazumichi Tsumura
IPC分类号： H01L21/288
CPC分类号： H01L21/76861 , H01L21/2885 , H01L21/76846 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method which includes forming a copper interconnect within a trench or via in a substrate. Forming the copper interconnect includes forming a ruthenium-containing seed layer on a wall of the trench or via; forming a cobalt sacrificial layer on the ruthenium-containing layer before the ruthenium-containing seed layer being exposed to an environment that is oxidizing with respect to the seed layer; and contacting the cobalt sacrificial layer with a copper plating solution, the copper plating solution dissolving the cobalt sacrificial layer and plating out copper on the unoxidized ruthenium-containing seed layer. Alternatively, the ruthenium-containing seed layer may be replaced with platinum, tungsten nitride, titanium nitride or titanium or iridium. Further alternatively, the cobalt sacrificial layer may be replaced by tin, cadmium, copper or manganese.
摘要翻译：公开了一种方法，其包括在衬底中的沟槽或通孔内形成铜互连。形成铜互连包括在沟槽或通孔的壁上形成含钌种子层; 在含钌种子层暴露于相对于种子层氧化的环境之前，在含钌层上形成钴牺牲层; 并且将钴牺牲层与铜电镀溶液接触，所述铜电镀溶液溶解钴牺牲层并在未氧化的含钌种子层上电镀铜。或者，可以用铂，氮化钨，氮化钛或钛或铱代替含钌种子层。此外，钴牺牲层可以被锡，镉，铜或锰替代。

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