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81. 发明授权

US07284649B2 Sheet feeding roller 失效
标题翻译：送纸辊
公开(公告)号：US07284649B2
公开(公告)日：2007-10-23
申请号：US11296450
申请日：2005-12-08
申请人： Keita Shiraki , Koji Yamaguchi
发明人： Keita Shiraki , Koji Yamaguchi
IPC分类号： B65G13/00
CPC分类号： G03G15/6529 , B65H27/00 , B65H2404/18 , B65H2701/1912 , G03G2215/00679 , G03G2215/00683
摘要： A sheet feeding roller, available at a lower cost, having lower hardness with securing both abrasion resistance and sustainability of friction coefficient. The sheet feeding roller comprises a hub, an inner layer provided on an outer peripheral surface of the hub, and an outer layer provided on an outer peripheral surface of the inner layer, the inner layer and the outer layer are formed by an unfoamed cured body of thermosetting urethane rubber wherein the outer layer is harder than the inner layer.
摘要翻译：以较低成本获得的片材进给辊具有较低的硬度，同时确保了摩擦系数的耐磨性和可持续性。片材进给辊包括轮毂，设置在轮毂的外周面上的内层和设置在内层的外周面上的外层，内层和外层由未发泡的固化体形成的热固性聚氨酯橡胶，其中外层比内层硬。

82. 发明申请

US20070218242A1 Surface-Coated Cutting Tool With Coated Film Having Strength Distribution of Compressive Stress 有权
标题翻译：表面涂层切割工具，涂层膜具有抗压应力的强度分布
公开(公告)号：US20070218242A1
公开(公告)日：2007-09-20
申请号：US10591458
申请日：2005-07-01
申请人： Hideki Moriguchi , Haruyo Fukui , Shinya Imamura , Koji Yamaguchi , Junji Iihara
发明人： Hideki Moriguchi , Haruyo Fukui , Shinya Imamura , Koji Yamaguchi , Junji Iihara
IPC分类号： B23B27/14
CPC分类号： C23C14/0641 , C23C30/005 , Y10T428/24 , Y10T428/24992 , Y10T428/31
摘要： A surface-coated cutting tool according to the present invention includes a base material and a coated film formed on the base material. The coated film serves as an outermost layer on the base material and has compressive stress. The compressive stress is varied so as to have strength distribution in a direction of thickness of the coated film. The strength distribution is characterized in that the compressive stress at a surface of the coated film continuously decreases from the surface of the coated film toward a first intermediate point located between the surface of the coated film and a bottom surface of the coated film and the compressive stress attains a relative minimum point at the first intermediate point.
摘要翻译：根据本发明的表面涂层切削工具包括基材和形成在基材上的涂膜。涂膜作为基材上的最外层，具有压应力。压缩应力变化，以便在涂膜的厚度方向上具有强度分布。强度分布的特征在于，涂膜表面的压缩应力从涂膜的表面朝向位于涂膜表面和涂膜底面之间的第一中间点连续减小，压缩应力在第一个中间点达到相对最小点。

83. 发明申请

US20070217815A1 Suspected place identifying apparatus and processing method 失效
标题翻译：疑似地点识别装置及处理方法
公开(公告)号：US20070217815A1
公开(公告)日：2007-09-20
申请号：US11492073
申请日：2006-07-25
申请人： Hiroaki Sato , Koji Yamaguchi
发明人： Hiroaki Sato , Koji Yamaguchi
IPC分类号： G03G21/16
CPC分类号： G06F11/079 , G06F11/0775
摘要： A statistically added point calculation unit of the present invention statistically adds a point to a part related to a content of an anomaly in error information received by an error information receiving unit, and sets the added point in an added point table. A suspected place identifying unit refers to the added point table, and if the statistically added point of a target of determination has exceeded a threshold, the suspected place identifying unit identifies the target of the determination as a suspected place. If the configuration information table is referred to and a target of this process is a maintenance part at the suspected place, the suspected place identifying unit compares an initial value, for example, by means of the threshold which has been doubled. Furthermore, the suspected place identifying unit identifies a part having the statistically added point which is the next highest, as a second suspected place. A part isolation processing unit isolates the part at the suspected place. A configuration information management unit sets a second suspected place flag at the corresponding part in the configuration information table.
摘要翻译：本发明的统计附加点计算单元对由错误信息接收单元接收到的错误信息中的异常内容的相关部分进行统计学上的加法，并将添加点设置在附加点表中。可疑位置识别单元是指附加点表，并且如果确定目标的统计添加点超过阈值，则怀疑地点识别单元将确定的目标识别为可疑地点。如果参考配置信息表，并且该处理的目标是在可疑位置处的维护部分，则可疑位置识别单元例如通过已经被加倍的阈值来比较初始值。此外，怀疑地点识别单元将具有下一最高的统计附加点的部分识别为第二可疑位置。部件隔离处理单元将部件隔离在可疑位置。配置信息管理单元在配置信息表中的相应部分设置第二可疑位置标志。

84. 发明授权

US07223634B2 Semiconductor device, method for manufacturing the same, circuit board, and electronic apparatus 有权
标题翻译：半导体装置及其制造方法，电路基板及电子设备
公开(公告)号：US07223634B2
公开(公告)日：2007-05-29
申请号：US10898174
申请日：2004-07-26
申请人： Koji Yamaguchi
发明人： Koji Yamaguchi
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/49816 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Exemplary embodiments of the present invention include a semiconductor device, a method for manufacturing the same, a circuit board and an electronic apparatus with increased productivity and reliability. An exemplary method for manufacturing a semiconductor device of the present invention includes forming a conductive part in a concave part on a first surface of a semiconductor substrate, the first surface having a plurality of chip mounting areas. Stacking at least one semiconductor chip in each of the chip mounting areas, providing a sealing member on the first surface of the semiconductor substrate and making part of a second surface of the semiconductor substrate thin so as to make the conductive part penetrate from the first surface to the second surface.
摘要翻译：本发明的示例性实施例包括具有提高的生产率和可靠性的半导体器件，其制造方法，电路板和电子设备。本发明的制造半导体器件的示例性方法包括在半导体衬底的第一表面上的凹部中形成导电部件，第一表面具有多个芯片安装区域。在每个芯片安装区域中堆叠至少一个半导体芯片，在半导体衬底的第一表面上提供密封构件，并使半导体衬底的第二表面的一部分变薄，以使导电部分从第一表面到第二个表面。

85. 发明申请

US20070029673A1 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument 有权
公开(公告)号：US20070029673A1
公开(公告)日：2007-02-08
申请号：US11544709
申请日：2006-10-10
申请人： Koji Yamaguchi
发明人： Koji Yamaguchi
IPC分类号： H01L23/48
CPC分类号： H05K3/3436 , H01L23/3114 , H01L23/49816 , H01L23/552 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/05001 , H01L2224/05022 , H01L2224/05184 , H01L2224/05548 , H01L2224/13099 , H01L2224/16 , H01L2224/16235 , H01L2924/0001 , H01L2924/01004 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H05K2201/09781 , Y02P70/613 , H01L2924/00 , H01L2224/05647 , H01L2924/00014 , H01L2224/05147 , H01L2224/05166
摘要： A semiconductor device includes a semiconductor substrate in which an integrated circuit is formed and which includes interconnects and electrodes, the interconnects electrically connected with the semiconductor substrate, and the electrodes being formed on the interconnects; a resin layer formed on the semiconductor substrate; redistribution interconnects electrically connected with the electrodes; a plurality of external terminals which are formed on the redistribution interconnects and supported by the resin layer; and a plurality of dummy terminals supported by the resin layer without being electrically connected with the electrodes.

86. 发明授权

US07132742B2 Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument 有权
公开(公告)号：US07132742B2
公开(公告)日：2006-11-07
申请号：US10637614
申请日：2003-08-11
申请人： Koji Yamaguchi
发明人： Koji Yamaguchi
IPC分类号： H01L23/12 , H01L23/053
CPC分类号： H05K3/3436 , H01L23/3114 , H01L23/49816 , H01L23/552 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/05001 , H01L2224/05022 , H01L2224/05184 , H01L2224/05548 , H01L2224/13099 , H01L2224/16 , H01L2224/16235 , H01L2924/0001 , H01L2924/01004 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H05K2201/09781 , Y02P70/613 , H01L2924/00 , H01L2224/05647 , H01L2924/00014 , H01L2224/05147 , H01L2224/05166
摘要： A semiconductor device includes a semiconductor substrate in which an integrated circuit is formed and which includes interconnects and electrodes, the interconnects electrically connected with the semiconductor substrate, and the electrodes being formed on the interconnects; a resin layer formed on the semiconductor substrate; redistribution interconnects electrically connected with the electrodes; a plurality of external terminals which are formed on the redistribution interconnects and supported by the resin layer; and a plurality of dummy terminals supported by the resin layer without being electrically connected with the electrodes.

87. 发明授权

US07127930B2 Device and method for press forming 失效
标题翻译：冲压成型装置及方法
公开(公告)号：US07127930B2
公开(公告)日：2006-10-31
申请号：US10471018
申请日：2002-02-15
申请人： Ichiro Ishii , Taizou Kitamura , Tokiyuki Wakayama , Koji Yamaguchi
发明人： Ichiro Ishii , Taizou Kitamura , Tokiyuki Wakayama , Koji Yamaguchi
IPC分类号： B21D13/02 , B21D37/00 , B21J13/03
CPC分类号： B21D13/02
摘要： A pressing apparatus includes a lower die (24) fixed to a lower plate (11), and first and second plate (11), and first and second upper die punches (33 and 34) capable of being lifted and lowered along with an upper plate (12). The first upper die punch (33) supported by a spring (49) is capable of being lifted and lowered relative to the second upper die punch (34). The upper plate (12) is lifted and lowered, while intermittently feeding a band-shaped work (W) one pitch by one pitch from the right to the left along an upper surface of the lower die (24), thereby pressing the work (W) to form grooves in the work (W) continuously. When the groove is formed in the work (W) by pressing the work (W) by the second upper die punch (34), the groove formed at the last time by pressing the work (W) by the second upper die punch (34) is retained and positioned between the first upper die punch (33) and the lower die (24). Therefore, the formation of the grove by the second upper die punch (34) can be carried out accurately.
摘要翻译：压紧装置包括固定在下板（11）上的下模（24）和第一和第二板（11），以及第一和第二上模冲头（33和34），能够与上板板（12）。由弹簧（49）支撑的第一上模冲头（33）能够相对于第二上模冲头（34）升高和降低。上板（12）被升降，同时沿着下模（24）的上表面间隔地从右向左一个间距地将带状工件（W）一个间距地供给一个间距，从而按压工件 W）连续地在工件（W）中形成凹槽。当通过第二上模冲头（34）对工件（W）进行加压而在工件（W）上形成槽时，通过第二上模冲头（34）对工件（W）进行加压而最后形成的槽）被保持并定位在第一上模冲头（33）和下模（24）之间。因此，可以精确地进行由第二上模冲头（34）形成的槽。

88. 发明申请

US20060086981A1 Power converter 有权
标题翻译：电源转换器
公开(公告)号：US20060086981A1
公开(公告)日：2006-04-27
申请号：US11254788
申请日：2005-10-21
申请人： Koji Yamaguchi , Yuuji Maeda , Tokihito Suwa , Satoru Sigeta
发明人： Koji Yamaguchi , Yuuji Maeda , Tokihito Suwa , Satoru Sigeta
IPC分类号： H01L27/12
CPC分类号： H02M7/003 , H01L2224/0603 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： The power converter for solving the above-described problem has a module section and a drive section for operating the module section. The drive section has a drive circuit. The drive circuit is provided so as to correspond to the first semiconductor element which is one of the semiconductor elements comprising the parallel circuit; wherein drive signals for operating the first semiconductor element are output. The drive signals that are output from the drive circuit are electrically branched and output to a second semiconductor element which is a separate semiconductor element from the first semiconductor element of the semiconductor elements comprising the parallel circuit. As a result, the second semiconductor element receives the branched drive signals and operates in the same manner as the first semiconductor element. Thereby, a motor converter favorable for control large current at a low cost is provided.
摘要翻译：用于解决上述问题的电力转换器具有用于操作模块部分的模块部分和驱动部分。驱动部分具有驱动电路。驱动电路被设置为对应于作为包括并联电路的半导体元件之一的第一半导体元件; 其中输出用于操作第一半导体元件的驱动信号。从驱动电路输出的驱动信号被电分支并输出到与包括并联电路的半导体元件的第一半导体元件分离的半导体元件的第二半导体元件。结果，第二半导体元件接收分支驱动信号并以与第一半导体元件相同的方式工作。因此，提供了一种有利于以低成本控制大电流的电机转换器。

89. 发明申请

US20060049840A1 Test probe and tester, method for manufacturing the test probe 有权
标题翻译：测试探针和测试仪，制造测试探针的方法
公开(公告)号：US20060049840A1
公开(公告)日：2006-03-09
申请号：US11184763
申请日：2005-07-19
申请人： Haruki Ito , Shinji Mizuno , Koji Yamaguchi
发明人： Haruki Ito , Shinji Mizuno , Koji Yamaguchi
IPC分类号： G01R31/02
CPC分类号： G09G3/006 , G01R1/06761 , G01R1/07314 , G09G3/3622 , Y10T29/49204
摘要： A test probe having a conductive part electrically connected to terminals of a test-object device, including: a silicon substrate; a protrusion made of resin provided on the silicon substrate; a first conductive part which is provided on the protrusion and comes in contact with the terminals; and a second conductive part which is provided in a region other than a region having the protrusion on the silicon substrate and is electrically connected to the first conductive part.
摘要翻译：一种测试探针，其具有与测试对象器件的端子电连接的导电部分，包括：硅衬底; 设置在硅基板上的由树脂制成的突起; 第一导电部，设置在突起上并与端子接触; 以及第二导电部，其设置在除了在所述硅基板上具有所述突起的区域以外的区域中，并且与所述第一导电部电连接。

90. 发明授权

US06969908B2 Semiconductor device, method of manufacturing the same, circuit board, and electronic instrument 失效
标题翻译：半导体装置及其制造方法，电路板和电子仪器
公开(公告)号：US06969908B2
公开(公告)日：2005-11-29
申请号：US10637615
申请日：2003-08-11
申请人： Koji Yamaguchi
发明人： Koji Yamaguchi
IPC分类号： H01L23/12 , H01L21/60 , H01L23/31 , H01L23/485 , H01L23/48 , H01L21/44 , H01L21/50 , H01L23/06
CPC分类号： H01L24/12 , H01L23/3114 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0231 , H01L2224/0401 , H01L2224/13099 , H01L2224/16 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor substrate has an integrated circuit, an interconnect electrically connected to the inside of the semiconductor substrate, and an electrode formed on the interconnect. A plurality of resin layers are separately formed on the semiconductor substrate so that part of the semiconductor substrate is exposed. A redistribution interconnect is electrically connected to the electrode. An external terminal is formed on the redistribution interconnect and supported by the resin layers.
摘要翻译：半导体衬底具有集成电路，电连接到半导体衬底的内部的互连以及形成在互连上的电极。在半导体基板上分开形成多个树脂层，使半导体基板的一部分露出。再分配互连电连接到电极。外部端子形成在再分布互连上并由树脂层支撑。

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