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81. 发明申请

US20100013049A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100013049A1
公开(公告)日：2010-01-21
申请号：US12504959
申请日：2009-07-17
申请人： Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Yoshiaki Fukuzumi , Masaru Kito , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Yoshiaki Fukuzumi , Masaru Kito , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yasuyuki Matsuoka
IPC分类号： H01L23/522 , H01L21/02 , H01L21/768
CPC分类号： H01L27/11578 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase shape, and a first interlayer dielectric film is formed around the first multilayer body. Next, a plurality of contact holes having a diameter decreasing downward are formed in the first interlayer dielectric film so that the contact holes reach respective end portions of the electrode films. Then, a sacrificial material is buried in the contact holes. Next, a second multilayer body is formed immediately above the first multilayer body, and a second interlayer dielectric film is formed around the second multilayer body. Thereafter, a plurality of contact holes having a diameter decreasing downward are formed in the second interlayer dielectric film to communicate with the respective contact holes formed in the first interlayer dielectric film. Then, the sacrificial material is removed and a contact is buried inside the contact holes. The contact has a step difference.
摘要翻译：通过在基板上交替层叠电介质膜和电极膜来形成第一多层体。然后，将第一多层体的端部加工成阶梯状，在第一层叠体的周围形成第一层间绝缘膜。接下来，在第一层间电介质膜中形成直径减小的多个接触孔，使得接触孔到达电极膜的各个端部。然后，牺牲材料被埋在接触孔中。接着，在第一多层体的正上方形成第二层叠体，在第二层叠体的周围形成第二层间绝缘膜。此后，在第二层间电介质膜中形成直径减小的多个接触孔，与形成在第一层间绝缘膜中的各接触孔连通。然后，去除牺牲材料并将接触件埋在接触孔内。联系人有差异。

82. 发明申请

US20090179257A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20090179257A1
公开(公告)日：2009-07-16
申请号：US12345088
申请日：2008-12-29
申请人： Yosuke Komori , Masaru Kito , Megumi Ishiduki , Ryota Katsumata , Hiroyasu Tanaka , Masaru Kidoh , Yoshiaki Fukuzumi , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Yosuke Komori , Masaru Kito , Megumi Ishiduki , Ryota Katsumata , Hiroyasu Tanaka , Masaru Kidoh , Yoshiaki Fukuzumi , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L29/792 , H01L21/762
CPC分类号： H01L29/792 , H01L21/8221 , H01L27/105 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/7926
摘要： A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.
摘要翻译：非挥发性半导体存储器件包括第一柱状半导体层和形成为使得用于存储电荷的电荷存储层夹在第一导电层和第一柱状半导体层之间的多个第一导电层。此外，非挥发性半导体存储器件包括第二柱状半导体层和形成为使得绝缘层夹在第二导电层和第二柱状半导体层之间的第二导电层，第二导电层重复地设置在一行中通过在与层叠方向垂直的第一方向上设置一定间隔来形成。沿着第二导电层的纵向方向在侧壁上形成与第二导电层接触并沿第一方向延伸的第一侧壁导电层。

83. 发明申请

US20110127597A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110127597A1
公开(公告)日：2011-06-02
申请号：US13003644
申请日：2009-07-01
申请人： Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Masaru Kito , Ryota Katsumata , Masaru Kidoh
发明人： Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Masaru Kito , Ryota Katsumata , Masaru Kidoh
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , G11C16/0466 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： A nonvolatile semiconductor memory device with charge storage layers with high reliability is provided. A plurality of insulating films and a plurality of electrode films 14 are alternately stacked on a substrate 11, and a plurality of selection gate electrodes 17 extending in the X direction and a plurality of bit lines BL extending in the Y direction are provided thereon. U-shaped silicon members 33 are provided, each of which is constituted by a plurality of silicon pillars 31 passing through the electrode films 14 and the selection gate electrode 17, whose upper ends are connected to the bit lines BL, and a connective member 32 connecting lower parts of one pair of the silicon pillars 31 disposed in diagonal positions. The electrode film 14 of each layer is divided for the respective selection gate electrodes 17. One pair of the silicon pillars 31 connected to one another through the connective member 32 are caused to pass through the different electrode films 14 and the different selection gate electrodes 17. All of the U-shaped silicon members 33 connected commonly to one bit line BL are commonly connected to another bit line BL.
摘要翻译：提供具有高可靠性的电荷存储层的非易失性半导体存储器件。多个绝缘膜和多个电极膜14交替堆叠在基板11上，并且在其上设置有沿X方向延伸的多个选择栅电极17和在Y方向上延伸的多个位线BL。设置有U形硅构件33，每个都由通过电极膜14的多个硅柱31和其上端连接到位线BL的选择栅电极17构成，并且连接构件32 连接设置在对角位置的一对硅柱31的下部。每个层的电极膜14被分配用于各个选择栅极电极17.使通过连接构件32彼此连接的一对硅柱31通过不同的电极膜14和不同的选择栅电极17 通常连接到一个位线BL的所有U形硅构件33共同连接到另一位线BL。

84. 发明申请

US20110215394A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110215394A1
公开(公告)日：2011-09-08
申请号：US12813895
申请日：2010-06-11
申请人： Yosuke Komori , Masaru Kidoh , Ryota Katsumata
发明人： Yosuke Komori , Masaru Kidoh , Ryota Katsumata
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/26 , H01L27/0688 , H01L27/11573
摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines. The plurality of local bit lines are connected to the channel body and commonly connected to the global bit line through the contact plug.
摘要翻译：根据一个实施例，半导体存储器件包括基底，层叠体，存储膜，通道体，接触塞，全局位线和多个局部位线。该基底具有形成于该基板上的基板和外围电路。层叠体具有交替地堆叠在基底上的多个导电层和绝缘层。记忆膜包括设置在层叠体的层叠方向形成的存储孔的内壁上的电荷存储膜。通道体设置在存储器孔内的记忆膜的内部。接触插塞是通过刺穿层叠体来提供的。全局位线设置在外围电路和层叠体之间并连接到接触插塞的下端部分。多个局部位线设置在堆叠体的上方并沿多个局部位线的延伸方向分割。多个局部位线连接到通道体并且通过接触插塞共同连接到全局位线。

85. 发明授权

US08288816B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08288816B2
公开(公告)日：2012-10-16
申请号：US12813895
申请日：2010-06-11
申请人： Yosuke Komori , Masaru Kidoh , Ryota Katsumata
发明人： Yosuke Komori , Masaru Kidoh , Ryota Katsumata
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/26 , H01L27/0688 , H01L27/11573
摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines. The plurality of local bit lines are connected to the channel body and commonly connected to the global bit line through the contact plug.
摘要翻译：根据一个实施例，半导体存储器件包括基底，层叠体，存储膜，通道体，接触塞，全局位线和多个局部位线。该基底具有形成于该基板上的基板和外围电路。层叠体具有交替地堆叠在基底上的多个导电层和绝缘层。记忆膜包括设置在层叠体的层叠方向形成的存储孔的内壁上的电荷存储膜。通道体设置在存储器孔内的记忆膜的内部。接触插塞是通过刺穿层叠体来提供的。全局位线设置在外围电路和层叠体之间并连接到接触插塞的下端部分。多个局部位线设置在堆叠体的上方并沿多个局部位线的延伸方向分割。多个局部位线连接到通道体并且通过接触插塞共同连接到全局位线。

86. 发明授权

US08723247B2 Semiconductor memory device and method for manufacturing same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08723247B2
公开(公告)日：2014-05-13
申请号：US13218972
申请日：2011-08-26
申请人： Yosuke Komori , Daigo Ichinose
发明人： Yosuke Komori , Daigo Ichinose
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/7926 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a plurality of gate electrode films arranged parallel to each other along a direction, a semiconductor member extending in the direction, and passing through the plurality of gate electrode films, and a charge storage film provided between the gate electrode films and the semiconductor member. Protrusions are provided projecting along the direction at the ends of the gate electrode films in opposition to the semiconductor member. A gaseous layer is formed in a part of a gap between the gate electrode films.
摘要翻译：根据一个实施例，半导体存储器件包括沿着方向彼此平行布置的多个栅极电极膜，沿该方向延伸的半导体部件，并且穿过多个栅极电极膜;以及电荷存储膜，栅极电极膜和半导体部件。沿着与半导体部件相对的栅极电极膜的端部的方向突出设置突起。在栅电极膜之间的间隙的一部分中形成气体层。

87. 发明授权

US07504772B2 Light-emitting diode array 有权
标题翻译：发光二极管阵列
公开(公告)号：US07504772B2
公开(公告)日：2009-03-17
申请号：US10793248
申请日：2004-03-05
申请人： Tomihisa Yukimoto , Eiichi Kunitake , Satoshi Sugiyama , Yosuke Komori , Toshimitsu Sukegawa
发明人： Tomihisa Yukimoto , Eiichi Kunitake , Satoshi Sugiyama , Yosuke Komori , Toshimitsu Sukegawa
IPC分类号： H05B33/04 , H05B33/10 , H01L29/18 , H01L33/00
CPC分类号： H01L27/153 , B41J2/45
摘要： A light-emitting diode array comprising a conductive layer formed on a substrate, separate light-emitting portions formed on the conductive layer, a first electrode formed on at least part of an upper surface of each light-emitting portion, and a second electrode formed on the conductive layer adjacent to the light-emitting portions; the first electrode comprising a common switching electrode matrix; the second electrode comprising a common electrode divided such that one second electrode exists in every block; and at least one of bonding pads extending to the first common electrode and the second common electrode being formed on a bonding portion formed on the conductive layer like an island, whereby the bonding pads are separate from each other.
摘要翻译：一种发光二极管阵列，包括形成在基板上的导电层，形成在导电层上的分离的发光部分，形成在每个发光部分的上表面的至少一部分上的第一电极和形成的第二电极在与发光部相邻的导电层上; 所述第一电极包括公共开关电极矩阵; 所述第二电极包括被分开以使得每个块中存在一个第二电极的公共电极; 并且至少一个延伸到第一公共电极的焊盘和第二公共电极形成在形成在导电层上的接合部分上，如岛状，由此焊盘彼此分离。

88. 发明授权

US08729623B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08729623B2
公开(公告)日：2014-05-20
申请号：US13423464
申请日：2012-03-19
申请人： Tomo Ohsawa , Yosuke Komori
发明人： Tomo Ohsawa , Yosuke Komori
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction. Each of the plurality of electrode layers is a first semiconductor layer containing a first impurity element. The diffusion suppressing layer is a second semiconductor layer containing a second impurity element which is different from the first impurity element. The diffusion suppressing layer is a film having an effect of suppressing diffusion of the first impurity element.
摘要翻译：根据一个实施例，一种非易失性半导体存储器件包括：堆叠体，包括交替堆叠的多个电极层和多个绝缘层，以及分别设置在多个电极层中的每一个之间的扩散抑制层，多个绝缘层; 以及设置在层叠方向上贯穿层叠体的孔的侧壁上的记忆膜。多个电极层中的每一个是包含第一杂质元素的第一半导体层。扩散抑制层是含有与第一杂质元素不同的第二杂质元素的第二半导体层。扩散抑制层是具有抑制第一杂质元素扩散的效果的膜。

89. 发明申请

US20060175620A1 Epitaxial wafer for light emitting diode 审中-公开
标题翻译：用于发光二极管的外延晶片
公开(公告)号：US20060175620A1
公开(公告)日：2006-08-10
申请号：US11269563
申请日：2005-11-09
申请人： Yosuke Komori
发明人： Yosuke Komori
IPC分类号： H01L33/00
CPC分类号： H01L33/0062
摘要： An epitaxial wafer for LED is provided with a layered structure by sequentially growing a p-type AlGaAs active layer 2, and a n-type AlGaAs window layer 1 on a p-type GaAs substrate 3 by liquid phase epitaxy (LPE) growth using Boat method. A maximum value of a dislocation density in a plane of the p-type type GaAs substrate is set within a range from 5,000 to 22,000 pcs/cm2. The epitaxial wafer for LED with low cost, excellent crystalline quality and high device quality can be obtained.
摘要翻译：通过液相外延（LPE）生长，使用船，在p型GaAs衬底3上依次生长p型AlGaAs有源层2和n型AlGaAs窗口层1，提供了用于LED的外延晶片的层状结构方法。 p型GaAs衬底的平面中的位错密度的最大值设定在5,000〜22,000个/ cm 2以上的范围内。可以获得低成本，优异的结晶质量和高的器件质量的用于LED的外延晶片。

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