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81. 发明授权

US5294882A Integrated circuit capable of testing reliability 失效
标题翻译：能够测试可靠性的集成电路
公开(公告)号：US5294882A
公开(公告)日：1994-03-15
申请号：US920659
申请日：1992-07-28
申请人： Junji Tanaka
发明人： Junji Tanaka
IPC分类号： G01R31/28 , G01R31/317 , G01R15/12
CPC分类号： G01R31/2856 , G01R31/31701
摘要： An integrated circuit having a predetermined function includes a signal generating circuit for generating a signal for performing a reliability test predetermined in the integrated circuit, a detecting circuit for outputting a signal which indicates a detection at a time when a rise of a supply voltage to the integrated circuit is detected, and a control circuit for controlling the integrated circuit so that a predetermined reliability test of the integrated circuit is performed by using the signal output from the signal generating circuit in case that a predetermined selection signal is applied to an input terminal of the control circuit in response to the signal output from the detecting circuit at a time of a rise of the supply voltage.
摘要翻译：具有预定功能的集成电路包括：信号发生电路，用于产生用于执行在集成电路中预定的可靠性测试的信号;检测电路，用于输出指示当电源电压上升时的检测的信号检测集成电路，以及控制电路，用于控制集成电路，使得在将预定的选择信号施加到输入端的输入端子的情况下，通过使用从信号发生电路输出的信号来执行集成电路的预定的可靠性测试所述控制电路响应于在所述电源电压上升时从所述检测电路输出的信号。

82. 发明授权

US5289063A Output circuit with buffer 失效
标题翻译：输出电路带缓冲器
公开(公告)号：US5289063A
公开(公告)日：1994-02-22
申请号：US960872
申请日：1992-10-14
申请人： Yukihisa Orisaka , Junji Tanaka , Yoshiki Sano
发明人： Yukihisa Orisaka , Junji Tanaka , Yoshiki Sano
IPC分类号： H03K17/16 , H03K17/04 , H03K17/687 , H03K19/017 , H03K19/0175 , H03K19/096
CPC分类号： H03K19/096 , H03K19/01742
摘要： An output circuit having a buffer, the buffer including the first transistor which receives at a gate thereof a periodic input voltage and the second transistor, the first and the second transistors being connected in series across a power line and a ground line, a junction of the first and second transistors being connected to an output terminal. The output circuit includes a circuit for applying, to a gate of the second transistor, a first voltage for the second transistor to serve as a bias transistor for charging a load connected to the output terminal with a voltage corresponding to the input voltage, and the second voltage greater than the first voltage for the second transistor to serve as a discharge transistor for discharging the load.
摘要翻译：一种具有缓冲器的输出电路，所述缓冲器包括在其栅极处接收周期性输入电压的第一晶体管和所述第二晶体管，所述第一和第二晶体管串联连接在电源线和接地线上，第一和第二晶体管连接到输出端子。输出电路包括用于向第二晶体管的栅极施加用于第二晶体管的第一电压以用作用于以与输入电压相对应的电压对连接到输出端子的负载充电的偏置晶体管的电路，大于第二晶体管的第一电压的第二电压用作用于放电负载的放电晶体管。

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