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    • 83. 发明授权
    • Method and apparatus for a parameterized interleaver design process
    • 用于参数化交织器设计过程的方法和装置
    • US08527833B2
    • 2013-09-03
    • US13231474
    • 2011-09-13
    • Rohit SeshadriMustafa ErozLin-Nan Lee
    • Rohit SeshadriMustafa ErozLin-Nan Lee
    • H03M13/00
    • H03M13/2767H03M13/275H03M13/276H03M13/2789
    • A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.
    • 提供了一种参数化的交织器设计过程,其优化了任何尺寸的交织器的设计,并且可以仅使用少量设计参数来完全指定。 根据参数化交织器设计处理,生成长度为N的交织器pi(i)。 定义了多个子鉴别掩码,并且将第一中间交织器置换分割成多个子组,其中子组的数量对应于子鉴别掩码的数量。 第一中间交织器排列的每个子组被划分成多个其他子组,并且每个子质量掩模被应用于第一中间交织器排列的相应子组的其他子组中的每一个,导致相应部分 第二中间交织器排列。 至少部分地基于第一和第二中间交织器排列来生成所产生的交织器pi(i)。
    • 85. 发明申请
    • METHOD AND SYSTEM FOR GENERATING LOW DENSITY PARITY CHECK CODES
    • 用于产生低密度奇偶校验码的方法和系统
    • US20080082895A1
    • 2008-04-03
    • US11938016
    • 2007-11-09
    • Mustafa ErozFreng-Wei SunLin-Nan Lee
    • Mustafa ErozFreng-Wei SunLin-Nan Lee
    • H03M13/00
    • H04L27/186H03M13/1111H03M13/112H03M13/1137H03M13/1165H03M13/152H03M13/255H03M13/2906H03M13/356H03M13/6583H04H40/90H04L1/00H04L1/005H04L1/0057H04L1/006H04L1/0061H04L1/0065H04L1/007H04L1/0071H04L27/2053
    • An approach for generating a structured Low Density Parity Check (LDPC) codes is provided. Structure of the LDPC codes is provided by restricting a certain part of the parity check matrix to be lower triangular, hence enabling a very simple encoding method that does not require the generator matrix of the code. The approach can also exploit the unequal error protecting capability of LDPC codes on transmitted bits to provide extra error protection to more vulnerable bits of high order modulation constellations (such as 8-PSK (Phase Shift Keying)). Additionally, an efficient decoding scheme is described where both bit nodes and check nodes are partitioned into groups. The edge values associated with each of the group can be placed together in memory simultaneously for bit nodes groups and check nodes groups. This architecture allows the multiple edges to be fetched from memory at a single clock cycle. A method of designing the parity check matrix that ensures the fetching of all the adjacent edges for a group of bit nodes or check nodes in a few clock cycles is described. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates.
    • 提供了一种用于生成结构化低密度奇偶校验(LDPC)码的方法。 通过将奇偶校验矩阵的某一部分限制为三角形来提供LDPC码的结构,因此能够实现不需要代码的生成矩阵的非常简单的编码方法。 该方法还可以利用LDPC码在传输比特上的不相等的差错保护能力,为高阶调制星座(如8-PSK(相移键控))的更脆弱的比特提供额外的错误保护。 另外,描述了一种有效的解码方案,其中比特节点和校验节点都被划分成组。 与组中的每个相关联的边缘值可以同时放置在存储器中用于位节点组和校验节点组。 该架构允许在单个时钟周期内从存储器中获取多个边。 描述了一种设计奇偶校验矩阵的方法,该矩阵确保在几个时钟周期内取出一组位节点或校验节点的所有相邻边缘。 上述方法特别适用于需要高数据速率的带宽受限通信系统。
    • 87. 发明授权
    • Method and apparatus for improved high order modulation
    • 用于改进高阶调制的方法和装置
    • US08674758B2
    • 2014-03-18
    • US13327316
    • 2011-12-15
    • Mustafa ErozLin-Nan Lee
    • Mustafa ErozLin-Nan Lee
    • H04L27/36H03C1/00H03C3/00H03D1/00H03D3/00
    • H04L27/34H04L1/004H04L1/0071H04L25/03312
    • Methods, systems and software are provided for high order signal modulation based on improved signal constellation and bit labeling designs for enhanced performance characteristics, including decreased power consumption. According to the improved signal constellation and bit labeling designs for enhanced performance characteristics, designs for 8-ary, 16-ary, 32-ary and 64-ary signal constellations are provided. According to an 8-ary constellation, improved bit labeling and bit coordinates are provided for a 1+7APSK signal constellation. According to a 16-ary constellation, improved bit labeling and bit coordinates are provided for a 6+10APSK signal constellation. According to three 32-ary constellations, improved bit labeling and bit coordinates are provided for a 16+16APSK signal constellation and two 4+12+16APSK signal constellations. According to two 64-ary constellations, improved bit labeling and bit coordinates are provided for an 8+16+20+20APSK signal constellation and a 12+16+16+20APSK signal constellation.
    • 提供了基于改进的信号星座图和位标签设计的用于高阶信号调制的方法,系统和软件,用于增强的性能特征,包括功耗降低。 根据改进的信号星座和位标签设计,增强了性能特征,提供了8路,16路,32路和64路信号星座的设计。 根据8位星座,为1 + 7APSK信号星座提供改进的比特标识和比特坐标。 根据16位星座,为6 + 10APSK信号星座提供了改进的比特标识和比特坐标。 根据三个32位星座,为16 + 16APSK信号星座和两个4 + 12 + 16APSK信号星座提供改进的比特标识和比特坐标。 根据两个64进制星座,为8 + 16 + 20 + 20APSK信号星座和12 + 16 + 16 + 20A + +信号星座提供改进的比特标识和比特坐标。
    • 89. 发明申请
    • METHOD AND APPARATUS FOR IMPROVED HIGH ORDER MODULATION
    • 改进高阶调制的方法和装置
    • US20130154755A1
    • 2013-06-20
    • US13327316
    • 2011-12-15
    • Mustafa ErozLin-Nan Lee
    • Mustafa ErozLin-Nan Lee
    • H03C3/00H03D3/00
    • H04L27/34H04L1/004H04L1/0071H04L25/03312
    • Methods, systems and software are provided for high order signal modulation based on improved signal constellation and bit labeling designs for enhanced performance characteristics, including decreased power consumption. According to the improved signal constellation and bit labeling designs for enhanced performance characteristics, designs for 8-ary, 16-ary, 32-ary and 64-ary signal constellations are provided. According to an 8-ary constellation, improved bit labeling and bit coordinates are provided for a 1+7APSK signal constellation. According to a 16-ary constellation, improved bit labeling and bit coordinates are provided for a 6+10APSK signal constellation. According to three 32-ary constellations, improved bit labeling and bit coordinates are provided for a 16+16APSK signal constellation and two 4+12+16APSK signal constellations. According to two 64-ary constellations, improved bit labeling and bit coordinates are provided for an 8+16+20+20APSK signal constellation and a 12+16+16+20APSK signal constellation.
    • 提供了基于改进的信号星座图和位标签设计的用于高阶信号调制的方法,系统和软件,用于增强的性能特征,包括功耗降低。 根据改进的信号星座和位标签设计,增强了性能特征,提供了8路,16路,32路和64路信号星座的设计。 根据8位星座,为1 + 7APSK信号星座提供改进的比特标识和比特坐标。 根据16位星座,为6 + 10APSK信号星座提供了改进的比特标识和比特坐标。 根据三个32位星座,为16 + 16APSK信号星座和两个4 + 12 + 16APSK信号星座提供改进的比特标识和比特坐标。 根据两个64进制星座,为8 + 16 + 20 + 20APSK信号星座和12 + 16 + 16 + 20A + +信号星座提供了改进的比特标识和比特坐标。