专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06451683B1 Damascene structure and method of making 有权
公开(公告)号：US06451683B1
公开(公告)日：2002-09-17
申请号：US09648465
申请日：2000-08-28
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L2906
CPC分类号： H01L21/76835 , H01L21/76807 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The selected low dielectric constant materials have similar methods of formation and similar capacities to withstand physical and thermal stress. In addition, the etchant used for each low dielectric constant insulating layer has a very small etching rate relative to the other low dielectric constant insulating layers. Thus, the low dielectric constant materials act as insulating layers through which trenches and vias are formed.

82. 发明授权

US06376370B1 Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy 有权
标题翻译：提供使用铝，铜，金和银冶金的种子层的方法
公开(公告)号：US06376370B1
公开(公告)日：2002-04-23
申请号：US09484002
申请日：2000-01-18
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76849 , H01L21/76859 , H01L21/76867 , H01L21/76874 , H01L21/76885 , H01L2221/1089
摘要： Structures and methods are provided which improve performance in integrated circuits. The structures and methods include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. According to the teachings of the present invention, the selective deposition of the metal lines avoids the need for multiple chemical mechanical planarization (CMP) steps. The low energy ion implantation of the present invention allows for the distinct placement of both the diffusion barrier and the seed layer. A residual resist can be used to remove the diffusion barrier and the seed layer from unwanted areas on a wafer surface. The novel methodology of the present invention includes patterning an insulator material to define a number of trenches in the insulator layer opening to a number of first level vias in a planarized surface. A barrier/adhesion layer is deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (e.v.) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. Structures formed by this novel process are similarly included within the scope of the present invention and account for aluminum, copper, gold, and silver metal interconnects.
摘要翻译：提供了提高集成电路性能的结构和方法。所述结构和方法包括在集成电路中的扩散阻挡层和种子层，它们均使用低能离子注入形成，然后选择性沉积用于集成电路的金属线。根据本发明的教导，金属线的选择性沉积避免了对多个化学机械平坦化（CMP）步骤的需要。本发明的低能量离子注入允许扩散阻挡层和籽晶层两者的不同放置。可以使用残余抗蚀剂来从晶片表面上的不需要的区域去除扩散阻挡层和种子层。本发明的新颖方法包括图案化绝缘体材料以限定在平坦化表面中开口到多个第一级通孔的绝缘体层中的多个沟槽。使用低能离子注入，例如，在多个沟槽中沉积阻挡层/粘合层。 100至800电子伏（e.v。）离子注入。种子层以也可使用低能离子注入的沟槽数量沉积在阻挡层/粘附层上。通过这种新方法形成的结构在本发明的范围内类似地包括在铝，铜，金和银金属互连中。

83. 发明授权

US06211049B1 Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals 有权
标题翻译：从金，银，铜和其他金属形成亚微米集成电路布线
公开(公告)号：US06211049B1
公开(公告)日：2001-04-03
申请号：US09256123
申请日：1999-02-24
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76874 , H01L21/76879 , H01L23/53228 , H01L23/53238 , H01L23/53242 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.
摘要翻译：典型的集成电路将数百万个微型晶体管和电阻器与埋在二氧化硅绝缘中的铝线互连。然而，铝线和二氧化硅绝缘是比金，银或铜线与聚合物基绝缘相结合的较不吸引人的组合，其承诺较低的电阻和电容以及因此更快，更有效的电路。不幸的是，常规的基于蚀刻的技术对于金，银或铜是无效的，并且常规的聚合物形成促进了与金属的反应，破坏了基于聚合物的绝缘体的绝缘性能。因此，本发明人设计了使用提升方法以避免蚀刻问题和非酸 - 聚合物前体和非氧化固化程序以保持聚合物绝缘体的绝缘性能的方法。所产生的互连结构有助于集成电路具有更好的速度和效率。

84. 发明授权

US06208016B1 Forming submicron integrated-circuit wiring from gold, silver, copper and other metals 有权
标题翻译：从金，银，铜和其他金属形成亚微米集成电路布线
公开(公告)号：US06208016B1
公开(公告)日：2001-03-27
申请号：US09256124
申请日：1999-02-24
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L2358
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76874 , H01L21/76879 , H01L23/53228 , H01L23/53238 , H01L23/53242 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.
摘要翻译：典型的集成电路将数百万个微型晶体管和电阻器与埋在二氧化硅绝缘中的铝线互连。然而，铝线和二氧化硅绝缘是比金，银或铜线与聚合物基绝缘相结合的较不吸引人的组合，其承诺较低的电阻和电容以及因此更快，更有效的电路。不幸的是，常规的基于蚀刻的技术对于金，银或铜是无效的，并且常规的聚合物形成促进了与金属的反应，破坏了基于聚合物的绝缘体的绝缘性能。因此，本发明人设计了使用提升方法以避免蚀刻问题和非酸 - 聚合物前体和非氧化固化程序以保持聚合物绝缘体的绝缘性能的方法。所产生的互连结构有助于集成电路具有更好的速度和效率。

85. 发明授权

US6077792A Method of forming foamed polymeric material for an integrated circuit 失效
标题翻译：形成用于集成电路的泡沫聚合材料的方法
公开(公告)号：US6077792A
公开(公告)日：2000-06-20
申请号：US892114
申请日：1997-07-14
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L21/312 , H01L21/316 , H01L21/768 , H01L21/469
CPC分类号： H01L21/312 , H01L21/31695 , H01L21/76801
摘要： A method of forming an insulating material for use in an integrated circuit includes providing a substrate of the integrated circuit and forming a polymeric material on the substrate. At least a portion of the polymeric material is converted to a foamed polymeric material. The converting of the polymeric material includes exposing at least a portion of the polymeric material to a supercritical fluid. Further, an integrated circuit includes a substrate of the integrated circuit and a foamed polymeric material on at least a portion of the substrate. The integrated circuit may further include a conductive layer adjacent the foamed polymeric material. The conductive layer may be a metal line on the foamed polymeric material, or the conductive layer may be an interconnect, e.g., a contact or a via, adjacent the foamed polymeric material.
摘要翻译：形成用于集成电路的绝缘材料的方法包括提供集成电路的基板并在基板上形成聚合材料。将至少一部分聚合物材料转化为泡沫聚合物材料。聚合材料的转化包括将至少一部分聚合物材料暴露于超临界流体。此外，集成电路包括集成电路的基板和在基板的至少一部分上的发泡聚合材料。集成电路还可以包括邻近发泡聚合物材料的导电层。导电层可以是发泡聚合物材料上的金属线，或者导电层可以是与发泡聚合材料相邻的互连，例如接触或通孔。

86. 发明授权

US5891797A Method of forming a support structure for air bridge wiring of an integrated circuit 失效
标题翻译：形成集成电路的气桥布线的支撑结构的方法
公开(公告)号：US5891797A
公开(公告)日：1999-04-06
申请号：US954450
申请日：1997-10-20
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L21/764 , H01L21/768 , H01L23/522
CPC分类号： H01L21/7682 , H01L21/764 , H01L23/5221 , H01L2924/0002
摘要： A process of manufacturing integrated circuits is disclosed for designing and implementing a hierarchical wiring system. The interconnection requirements are sorted and designed into a particular wiring level according to length. Support structures may be constructed to allow more flexibility in designing air bridge dimensions. The support structures may take the form of lateral ribs or intermediate posts, and may be fabricated of either insulating or conductive material. One integrated circuit described is a memory device, such as a dynamic random access memory.
摘要翻译：公开了用于设计和实现分层布线系统的集成电路的制造工艺。互连要求根据长度被分类和设计成特定的布线层。可以构造支撑结构以允许在设计空气桥尺寸时具有更大的灵活性。支撑结构可以采取横向肋或中间柱的形式，并且可以由绝缘或导电材料制成。所描述的一个集成电路是诸如动态随机存取存储器的存储器件。

87. 发明授权

US5313097A High density memory module 失效
标题翻译：高密度内存模块
公开(公告)号：US5313097A
公开(公告)日：1994-05-17
申请号：US976770
申请日：1992-11-16
申请人： Javad Haj-Ali-Ahmadi , Paul A. Farrar , Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Jacqueline A. Shorter-Beauchamp , John A. Williamson
发明人： Javad Haj-Ali-Ahmadi , Paul A. Farrar , Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Jacqueline A. Shorter-Beauchamp , John A. Williamson
IPC分类号： H01L25/00 , H01L25/065 , H01L25/07 , H01L25/18 , H05K3/32 , H01L23/02 , H02B1/00
CPC分类号： H01L25/0657 , H01L25/0652 , H05K3/325 , H01L2224/16 , H01L2224/16108 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06596
摘要： A memory module is built up from a power distribution assembly in the form of plates forming a capacitor of low inductance and a flexible circuit substrate. The circuit substrate is populated with precisely positioned contact pads for the power, read, write and address lines of memory chips that contact the substrate. Memory chips are fixed to heat spreaders and loaded into a chip holder which positions the chips for contact with the contact pads on the substrate. The substrate contact pads are plated to form dendritic crystals of palladium and the memory chips are provided with solder balls on the contact pads of the memory chip. The solder balls are held in contact with the contact pads by the compressive forces of clamping a heat sink over the heat spreaders for testing, and the assembly may be readily disassembled to replace any defective memory. The compression connection of the chips to the substrate may be relied on or the solder balls may be reflowed to establish permanent solder connections.
摘要翻译：存储器模块由形成低电感电容器的板的形式的配电组件和柔性电路基板构成。电路基板上装有用于接触基板的存储芯片的功率，读取，写入和地址线的精确定位的接触焊盘。存储芯片固定在散热器上，并装载到芯片保持器中，芯片保持器将芯片定位成与衬底上的接触焊盘接触。将衬底接触垫电镀以形成钯的树枝晶体，并且存储器芯片在存储器芯片的接触焊盘上设置有焊球。通过将散热器夹在散热器上用于测试的压缩力，焊球与接触垫保持接触，并且组装可以容易地拆卸以代替任何有缺陷的存储器。芯片与基板的压缩连接可以依赖于或者焊球可以被回流以建立永久的焊接连接。

88. 发明授权

US07745934B2 Integrated circuit and seed layers 有权
标题翻译：集成电路和种子层
公开(公告)号：US07745934B2
公开(公告)日：2010-06-29
申请号：US12145382
申请日：2008-06-24
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L23/48 , H01L21/302
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76849 , H01L21/76859 , H01L21/76867 , H01L21/76874 , H01L21/76885 , H01L2221/1089
摘要： Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit. Apparatus and systems having such structures and methods of forming these structures for apparatus and systems are disclosed.
摘要翻译：提供了包括设置在集成电路中的扩散阻挡层和种子层的分层布置上的导电层的结构。公开了具有用于装置和系统形成这些结构的这种结构和方法的装置和系统。

89. 发明授权

US07614027B2 Methods for forming a MRAM with non-orthogonal wiring 有权
标题翻译：用非正交布线形成MRAM的方法
公开(公告)号：US07614027B2
公开(公告)日：2009-11-03
申请号：US11383905
申请日：2006-05-17
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： G06F17/50
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/20 , G03F1/78 , G03F7/70383 , G03F7/70533 , H01J37/3174 , H01J2237/30488 , H01L27/0207 , H01L27/222 , Y02P90/265
摘要： The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. Various method embodiments relate to forming a magnetic random access memory (MRAM) array. Various embodiments include forming a first wiring layer of approximately parallel conductors, a second wiring layer of approximately parallel conductors and a third wiring layer of approximately parallel conductors such that the first, second and third wiring layers cross at a number of intersections. At least one of the first, second and third wiring layers are formed so as to be non-orthogonal with respect to a remaining at least one of the first, second and third wiring layers. The method further includes forming a layer of magnetic storage elements proximately located to the intersections. Other aspects are provided herein.
摘要翻译：本主题允许以与正交线相同的厚度形成非正交线，从而促进紧凑的设计，形成均匀的线边缘，并且有效地形成。各种方法实施例涉及形成磁随机存取存储器（MRAM）阵列。各种实施例包括形成大致平行的导体的第一布线层，大致平行的导体的第二布线层和大致平行的导体的第三布线层，使得第一布线层和第三布线层在多个交点处交叉。第一，第二和第三布线层中的至少一个形成为相对于第一，第二和第三布线层中剩余的至少一个布线不正交。该方法还包括形成一个靠近相交处的磁存储元件层。本文提供了其他方面。

90. 发明申请

US20090179331A1 INTEGRATED CIRCUIT INSULATORS AND RELATED METHODS 有权
标题翻译：集成电路绝缘子及相关方法
公开(公告)号：US20090179331A1
公开(公告)日：2009-07-16
申请号：US12406532
申请日：2009-03-18
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first structural material upon a substrate, the first structural material having sufficient mechanical characteristics to support metal during chemical-mechanical polishing (CMP). The method also includes depositing a metallic layer upon the insulating layer, the metallic layer adapted to be used as a wiring channel. The method further includes processing the metallic layer to form the wiring channel, where processing includes CMP. In addition, the method includes removing and replacing at least a portion of the first structural material with a second structural material, the second structural material having insufficient mechanical characteristics to support metal during CMP. Other aspects and embodiments are provided herein.
摘要翻译：提供了一种用于在集成电路中提供低介电常数绝缘体的系统和方法。本公开的一个方面涉及一种用于形成集成电路绝缘体的方法。该方法包括在基板上使用第一结构材料形成绝缘层，第一结构材料在化学机械抛光（CMP）期间具有足够的机械特性来支撑金属。该方法还包括在绝缘层上沉积金属层，金属层适于用作布线通道。该方法还包括处理金属层以形成布线沟道，其中处理包括CMP。此外，该方法包括用第二结构材料去除和替换第一结构材料的至少一部分，第二结构材料在CMP期间具有不足的机械特性以支撑金属。本文提供了其它方面和实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式