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81. 发明授权

US07084449B2 Microelectronic element having trench capacitors with different capacitance values 失效
标题翻译：具有不同电容值的沟槽电容器的微电子元件
公开(公告)号：US07084449B2
公开(公告)日：2006-08-01
申请号：US10710146
申请日：2004-06-22
申请人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
发明人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
IPC分类号： H01L27/108 , H01L29/00
CPC分类号： H01L29/66181 , H01L27/1087 , H01L27/10894 , H01L29/945
摘要： A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.
摘要翻译：提供具有主表面的微电子元件，微电子元件包括形成在第一沟槽的侧壁上的第一电容器，第一沟槽从主表面沿向下延伸的方向伸长。微电子元件还包括形成在第二沟槽的侧壁上的第二电容器，第二沟槽从主表面沿向下延伸的方向伸长，其中第一电容器的顶部设置在距离主表面的第一深度处，并且第二电容器的顶部设置在距离主表面的第二深度处。

82. 发明授权

US07009237B2 Out of the box vertical transistor for eDRAM on SOI 有权
标题翻译：在SOI上用于eDRAM的开箱式垂直晶体管
公开(公告)号：US07009237B2
公开(公告)日：2006-03-07
申请号：US10709450
申请日：2004-05-06
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译：本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件掩埋氧化层。上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

83. 发明授权

US06943409B1 Trench optical device 有权
标题翻译：沟槽光学器件
公开(公告)号：US06943409B1
公开(公告)日：2005-09-13
申请号：US10709699
申请日：2004-05-24
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/76
CPC分类号： B82Y20/00 , H01L27/1446 , H01L31/03529 , H01L31/105 , H01L31/1804 , Y02E10/547
摘要： A semiconductor device is formed in on a semiconductor substrate starting with a first step, which is to form a wide trench and a narrow trench in the substrate. Then form a first electrode in the narrow trench by depositing a first fill material of a first conductivity type over the device to fill the wide trench partially and to fill the narrow trench completely. Etch back the first fill material until completion of removal thereof from the wide trench. Form a second electrode in the wide trench by filling the wide trench with a second fill material of an opposite conductivity type. Anneal to drive dopant both from the first fill material of the first electrode into a first outdiffusion region in the substrate about the periphery of the narrow trench and from the second fill material of the second electrode into a second outdiffusion region in the substrate about the periphery of the wide trench.
摘要翻译：半导体器件形成在半导体衬底上，从第一步骤开始，其在衬底中形成宽沟槽和窄沟槽。然后通过在器件上沉积第一导电类型的第一填充材料，以便部分填充宽沟槽并完全填充窄沟槽，在窄沟槽中形成第一电极。将第一填充材料回扫，直到完成从宽沟槽中移除。通过用相反导电类型的第二填充材料填充宽沟槽在宽沟槽中形成第二电极。退火以将掺杂剂从第一电极的第一填充材料驱动到衬底周围的窄沟槽的第一外扩散区域中，并且从第二电极的第二填充材料移动到衬底周围的第二外扩散区域的宽沟。

84. 发明授权

US06759702B2 Memory cell with vertical transistor and trench capacitor with reduced burried strap 有权
标题翻译：具有垂直晶体管和沟槽电容器的存储单元，具有减少的挂带
公开(公告)号：US06759702B2
公开(公告)日：2004-07-06
申请号：US10261559
申请日：2002-09-30
申请人： Carl J. Radens , Ramachandra Divakaruni , Jack A. Mandelman
发明人： Carl J. Radens , Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/66181 , H01L29/945
摘要： A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions. The deep trench has a perimeter in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter, and being less than one lithographic feature size. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The structure is particularly useful for a sub-8F2 cell.
摘要翻译：一种存储单元结构，包括半导体衬底，半导体衬底中的深（例如，纵向）沟槽，深沟槽具有多个侧壁和底部，沿着深沟槽的侧壁的掩埋带，存储电容器深沟槽的底部，垂直晶体管，沿着存储电容器上方的深沟槽的侧壁向下延伸，晶体管具有在衬底的与深沟槽相邻的平面中延伸的扩散，从深沟槽的另一个侧壁延伸的环状氧化物与电容器相对的浅沟槽隔离区域沿垂直于垂直晶体管延伸的侧壁横向的衬底表面延伸，在深沟槽内延伸的栅极导体，延伸在深沟槽上并与栅极导体连接的字线以及在衬底的表面平面上方延伸的位线，该位线与浅沟槽iso之间的扩散接触国际地区。深沟槽在垂直于其深度的方向上具有周长，并且掩埋带沿着周边延伸一段距离，该距离仅在沿着周边的整个线性距离的5％至20％的范围内，并且更小比一个光刻特征尺寸。优选地，沿着周边的方向上的带子是弯曲的并且沿着周边的一个角部设置。该结构对于亚8F 2细胞特别有用。

85. 发明授权

US06730552B1 MOSFET with decoupled halo before extension 有权
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US06730552B1
公开(公告)日：2004-05-04
申请号：US10604096
申请日：2003-06-26
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Carl J. Radens , William R. Tonti
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

86. 发明授权

US06720630B2 Structure and method for MOSFET with metallic gate electrode 有权
标题翻译：具有金属栅电极的MOSFET的结构和方法
公开(公告)号：US06720630B2
公开(公告)日：2004-04-13
申请号：US09867874
申请日：2001-05-30
申请人： Jack A. Mandelman , Oleg Gluschenkov , Carl J. Radens
发明人： Jack A. Mandelman , Oleg Gluschenkov , Carl J. Radens
IPC分类号： H01L2976
CPC分类号： H01L21/28247 , H01L29/4933 , H01L29/6653 , H01L29/66545 , H01L29/6659 , Y10S257/90
摘要： A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifically, the inventive semiconductor structure includes a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, the patterned gate region includes at least a metallic gate electrode formed atop a polysilicon gate electrode; hanging sidewall spacers formed on an upper portion of the patterned gate region including the metallic gate electrode; and a thermal oxide layer formed on lower portions of patterned gate region including a portion of the polysilicon gate electrode, but not the metallic gate electrode.
摘要翻译：提供一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法，该金属氧化物半导体场效应晶体管（MOSFET）具有金属栅电极，其在随后的栅极氧化处理期间被悬挂的侧壁间隔物保护。还提供了通过本发明方法形成的半导体结构。具体地，本发明的半导体结构包括半导体衬底，其包括形成在图案化栅极电介质上的图案化栅极区域，所述图案化栅极区域至少包括形成在多晶硅栅电极顶部的金属栅电极; 形成在包括金属栅极的图案化栅极区域的上部上的悬挂侧壁间隔物; 以及形成在图案化栅极区域的下部上的热氧化物层，其包括多晶硅栅电极的一部分而不是金属栅电极。

87. 发明授权

US06674139B2 Inverse T-gate structure using damascene processing 失效
标题翻译：使用镶嵌加工的逆T型栅结构
公开(公告)号：US06674139B2
公开(公告)日：2004-01-06
申请号：US09910636
申请日：2001-07-20
申请人： Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28114 , H01L29/42368 , H01L29/66492 , H01L29/66537 , H01L29/66553 , H01L29/66583 , H01L29/66598 , H01L29/66666
摘要： A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.
摘要翻译：场效应晶体管具有具有较厚中心部分和较薄翼的逆T栅极导体。翼可以是与中心部分不同的材料。此外，栅极电介质可以沿着边缘比在中心更厚。翅膀下的掺杂也可以不同于沿着中心部分或超出门。机翼下方的区域可能与栅极导体的掺杂不同。利用基本上垂直的注入，在不注入沟道的中心部分的情况下注入与栅极的边缘重叠的沟道的区域，并且阻止该区域接收栅电极的所接收的较厚部分的至少一部分。

88. 发明授权

US06576945B2 Structure and method for a compact trench-capacitor DRAM cell with body contact 失效
公开(公告)号：US06576945B2
公开(公告)日：2003-06-10
申请号：US09777576
申请日：2001-02-05
申请人： Jack A. Mandelman , Carl J. Radens
发明人： Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/1203
摘要： A compact DRAM cell array that substantially minimizes floating-body effects and device-to-device interactions is disclosed. The compact DRAM cell array includes a plurality of annular memory cells that are arranged in rows and columns. Each annular memory cell includes a vertical MOSFET and an underlying capacitor that are in electrical contact to each other through a buried-strap outdiffusion region which is present within a portion of a wall of each annular memory cell such that the portion partially encircles the wall. The remaining portions of the wall of each annular memory cell have a body contact region that serves to electrically connect the annular memory cell to an adjacent array well region. The DRAM cell array also includes a plurality of wordlines overlaying the vertical MOSFETs, and a plurality of bitlines that are orthogonal to the plurality of wordlines.

89. 发明授权

US06566177B1 Silicon-on-insulator vertical array device trench capacitor DRAM 有权
标题翻译：绝缘体上的垂直阵列器件沟槽电容器DRAM
公开(公告)号：US06566177B1
公开(公告)日：2003-05-20
申请号：US09427257
申请日：1999-10-25
申请人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
发明人： Carl J. Radens , Gary B. Bronner , Tze-chiang Chen , Bijan Davari , Jack A. Mandelman , Dan Moy , Devendra K. Sadana , Ghavam Ghavami Shahidi , Scott R. Stiffler
IPC分类号： H01L2100
CPC分类号： H01L27/10864 , H01L27/1087
摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.
摘要翻译：一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。掩埋氧化层将SOI层与硅衬底隔离。沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。最初，在晶圆中形成掩埋氧化物层。深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。在沟槽中形成保护侧壁。然后，将深沟槽蚀刻到衬底中。衬底中的体积被扩大以形成瓶形沟槽。在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。浅沟槽隔离（STI）用于隔离和定义细胞。在晶片上形成位线和字线。

90. 发明授权

US06429474B1 Storage-capacitor electrode and interconnect 失效
标题翻译：储存电容电极和互连
公开(公告)号：US06429474B1
公开(公告)日：2002-08-06
申请号：US09547335
申请日：2000-04-11
申请人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
发明人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L23/522 , H01L27/10894 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括与存储电容器的各个板同时形成的下电容器电极和上电容器电极。两个电容器电极可用于在DRAM单元阵列内形成不同的互连。

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