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    • 84. 发明授权
    • Automatic failover during online data migration
    • 在线数据迁移期间自动故障切换
    • US08392753B1
    • 2013-03-05
    • US12750391
    • 2010-03-30
    • Arieh DonIan WigmoreMichael SpechtSteven GoldbergVaishali Kochavara
    • Arieh DonIan WigmoreMichael SpechtSteven GoldbergVaishali Kochavara
    • G06F11/07
    • G06F11/1662G06F11/2094
    • A technique automatically handles a failure during online data migration from a source array to a target array. While a host initially accesses data from the source array using multipath I/O software, the technique involves (i) transitioning the source array to a passive mode, and the target array to an active mode, and (ii) beginning a data transfer operation which transfers data from the source array to the target array. The technique further involves modifying the data on both the target array and the source array in response to modification commands sent to the target array from the host while the data transfer operation is ongoing. The technique further involves automatically failing back to providing access to the data from the source array in response to an event in which the target array loses communication with the source array for a predefined amount of time.
    • 在从源阵列到目标阵列的在线数据迁移过程中,技术自动处理故障。 主机最初使用多路径I / O软件从源阵列访问数据,该技术涉及(i)将源阵列转换为被动模式,将目标阵列转换为活动模式,以及(ii)开始数据传输操作 它将数据从源数组传输到目标数组。 该技术还涉及在数据传送操作正在进行时响应于从主机发送到目标阵列的修改命令来修改目标阵列和源阵列上的数据。 该技术进一步涉及自动失败以响应于目标阵列在预定义的时间量内与源阵列失去通信的事件来提供对来自源阵列的数据的访问。
    • 90. 发明申请
    • Memory cell arrangements and methods of manufacturing memory cell arrangements
    • 存储单元布置和制造存储单元布置的方法
    • US20080073694A1
    • 2008-03-27
    • US11526149
    • 2006-09-22
    • Josef WillerThomas MikolajickNicolas NagelMichael Specht
    • Josef WillerThomas MikolajickNicolas NagelMichael Specht
    • H01L29/788
    • H01L27/105H01L27/11526H01L27/11529
    • A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.
    • 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串,其中至少一些是存储单元;第二存储单元串,具有多个串联的源至漏耦合的晶体管 晶体管,其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。