专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US08140731B2 System for data processing using a multi-tiered full-graph interconnect architecture 失效
标题翻译：使用多层全图互连架构进行数据处理的系统
公开(公告)号：US08140731B2
公开(公告)日：2012-03-20
申请号：US11845206
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
IPC分类号： G06F13/14
CPC分类号： G06F15/16
摘要： A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
摘要翻译：提供了一种用于实现多层全图互连架构的系统。为了实现多层全图互连架构，多个处理器彼此耦合以创建多个处理器书籍。多个处理器书联接在一起以创建多个超节点。然后，将多个超节点耦合在一起以创建多层全图互连体系结构。然后，数据在多层全图互连体系结构中从一个处理器传输到另一个处理器，这是基于一个寻址方案，该寻址方案至少指定了一个与要发送数据的目标处理器相关联的超级节点和一个处理器。

82. 发明授权

US08117401B2 Interconnect operation indicating acceptability of partial data delivery 有权
标题翻译：互连操作指示部分数据传送的可接受性
公开(公告)号：US08117401B2
公开(公告)日：2012-02-14
申请号：US12024467
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0886 , G06F2212/1016
摘要： According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request.
摘要翻译：根据至少一个实施例，多处理器数据处理系统中的数据处理方法包括请求处理单元发起包括存储器访问请求的互连操作，所述存储器访问请求指示可变数量的数据的可接受性来维护数据的互连请求。响应于在互连上窥探存储器访问请求，窥探者选择要提供给请求处理单元的数据量，并将所选择的数据量发送到请求处理单元。请求处理单元接收所选择的数据量并利用所选择的数量的数据中的至少一些来处理处理器请求。

83. 发明授权

US08108545B2 Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture 失效
标题翻译：分组聚合在多层全图互连架构中的数据处理系统的虚拟通道中
公开(公告)号：US08108545B2
公开(公告)日：2012-01-31
申请号：US11845227
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F15/16 , G06F15/173 , H04L12/43 , H04L1/18
CPC分类号： H04L67/10 , H04L69/40
摘要： A mechanism is provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data into a data packet to be transmitted to a destination processor, the original data comprising payload data and overhead data. The first processor transmits the data packet to a second processor along a path to the destination processor. The second processor determines if the second processor has additional payload data destined for the same destination processor. Responsive to the second processor having the additional payload data, the second processor unbundles the data packet, adds the additional payload data to the payload data, and rebundles the payload data along with the additional payload data and the overhead data into a rebundled data packet. Then the second processor transmits the rebundled data packet to at least one other processor along the path to the destination processor.
摘要翻译：提供了一种用于数据处理系统的虚拟通道中的分组聚合的机制。第一处理器将原始数据捆绑到要发送到目的处理器的数据分组中，原始数据包括有效载荷数据和开销数据。第一处理器沿着到目的地处理器的路径向第二处理器发送数据分组。第二处理器确定第二处理器是否具有去往相同目的地处理器的附加有效载荷数据。响应于具有附加有效载荷数据的第二处理器，第二处理器解除数据分组的捆绑，将附加的有效载荷数据添加到有效载荷数据，并将有效载荷数据连同额外的有效载荷数据和开销数据重新分组成重新绑定的数据分组。然后，第二处理器将重新发送的数据分组传送到至少一个其他处理器，沿着到达目的地处理器的路径。

84. 发明授权

US08077602B2 Performing dynamic request routing based on broadcast queue depths 失效
标题翻译：基于广播队列深度执行动态请求路由
公开(公告)号：US08077602B2
公开(公告)日：2011-12-13
申请号：US12024514
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/28 , H04L12/56
CPC分类号： G06F15/17
摘要： Mechanisms for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译：提供了基于广播深度队列信息执行动态请求路由的机制。系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供队列深度信息。队列深度信息识别发起心跳信号的处理器芯片的每个队列中的数量的请求或数据量。系统中每个处理器芯片的队列深度信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

85. 发明授权

US07958309B2 Dynamic selection of a memory access size 有权
标题翻译：动态选择内存访问大小
公开(公告)号：US07958309B2
公开(公告)日：2011-06-07
申请号：US12024476
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F12/0886 , G06F12/0831 , G06F2212/1016 , G06F2212/502
摘要： A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.
摘要翻译：由存储器层级支持的处理单元中的数据处理方法包括执行对存储器层次的多个存储器访问的处理单元。多个存储器访问包括针对全缓存数据行的一个或多个存储器访问。处理单元监视由多个存储器访问访问的数据的利用，并且基于数据的利用，动态地改变存储器访问操作模式，使得后续存储修改存储器访问目标小于完整高速缓存行数据。

86. 发明授权

US07840703B2 System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture 有权
标题翻译：在多层全图互连体系结构中动态支持间接路由的系统和方法
公开(公告)号：US07840703B2
公开(公告)日：2010-11-23
申请号：US11845213
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F15/16
CPC分类号： G06F15/17381 , H04L45/00 , H04L45/02 , H04L45/122 , H04L45/125 , H04L67/327
摘要： A method, computer program product, and system are provided for dynamically routing data through the data processing system. Data is received at a first processor that is to be transmitted to a destination processor. The data that is received includes address information. A lookup is performed in routing table data structures based on the address information to identify candidate paths through which the data is routed to the destination processor. A determination is made as to whether any of the candidate paths are not able to be used to route the data to the destination processor based on a setting of at least one identifier. A path is selected from the identified candidate paths for routing of the data based on a setting of the at least one identifier. Then, the data is transmitted from the first processor along the selected path toward the destination processor.
摘要翻译：提供了一种通过数据处理系统动态路由数据的方法，计算机程序产品和系统。在要发送到目的处理器的第一处理器处接收数据。接收的数据包括地址信息。基于地址信息在路由表数据结构中执行查找，以识别数据被路由到目的地处理器的候选路径。基于至少一个标识符的设置，确定是否有任何候选路径不能用于将数据路由到目的地处理器。基于所述至少一个标识符的设置，从所识别的候选路径中选择路径以路由数据。然后，数据从所选择的路径从第一处理器发送到目的处理器。

87. 发明授权

US07809970B2 System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture 有权
标题翻译：用于在多层全图互连架构中提供用于屏障操作的高速消息传递接口的系统和方法
公开(公告)号：US07809970B2
公开(公告)日：2010-10-05
申请号：US11845225
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F1/12 , G06F1/32
CPC分类号： G06F9/5088
摘要： A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.
摘要翻译：提供了一种执行消息传递接口（MPI）作业的方法，计算机程序产品和系统。第一处理器芯片从数据处理系统中执行MPI作业的任务的一组处理器芯片接收一组到达信号。到达信号确定处理器芯片何时执行用于同步MPI作业任务的同步操作。响应于从该组处理器芯片接收到一组到达信号，第一处理器芯片标识出到达信号到达第一个处理器芯片组中最快的处理器芯片。基于最快处理器芯片的识别，修改最快处理器芯片的操作。该组处理器芯片包括位于数据处理系统的相同处理器簿或不同处理器簿之一中的处理器芯片。

88. 发明授权

US07779148B2 Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips 有权
标题翻译：基于在广播心跳信号中接收到的未响应的活动源请求数量的信息进行动态路由并存储在其他处理器芯片的本地数据结构中
公开(公告)号：US07779148B2
公开(公告)日：2010-08-17
申请号：US12024553
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F15/163
CPC分类号： H04L45/122 , H04L45/06
摘要： A mechanism for performing dynamic request routing based on broadcast source request information is provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译：提供了一种基于广播源请求信息进行动态请求路由的机制。系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

89. 发明申请

US20100070711A1 Techniques for Cache Injection in a Processor System Using a Cache Injection Instruction 有权
标题翻译：使用缓存注入指令的处理器系统中缓存注入的技术
公开(公告)号：US20100070711A1
公开(公告)日：2010-03-18
申请号：US12212935
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0862 , G06F3/0604 , G06F3/061 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0835 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.
摘要翻译：用于执行高速缓存注入的技术包括响应于高速缓存注入指令监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于与高速缓存注入指令相关联的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

90. 发明申请

US20090198920A1 Processing Units Within a Multiprocessor System Adapted to Support Memory Locks 审中-公开
标题翻译：适用于支持内存锁的多处理器系统中的处理单元
公开(公告)号：US20090198920A1
公开(公告)日：2009-08-06
申请号：US12024234
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F15/16 , G06F9/3004 , G06F9/30087 , G06F9/526
摘要： A processing unit within a multiprocessor system adapted to support memory locks is disclosed. In response to a request for accessing a data block being denied when a lock control section of the data block has been set by a memory controller, a timer countdown is started within a processing unit within a multiprocessor system. The requesting processing unit can relinquish the access request once the timer countdown has reached a timeout period.
摘要翻译：公开了一种适于支持存储器锁的多处理器系统内的处理单元。响应于当由存储器控制器设置数据块的锁定控制部分时访问被拒绝的数据块的请求，在多处理器系统内的处理单元内启动定时器倒计时。一旦定时器倒计时达到超时时间，请求处理单元可以放弃访问请求。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式