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    • 81. 发明授权
    • Apparatus for decoding BCH code for correcting complex error
    • 用于对用于校正复杂错误的BCH码进行解码的装置
    • US5420873A
    • 1995-05-30
    • US844159
    • 1992-04-06
    • Atsuhiro YamagishiTouru InoueTokumichi MurakamiKohtaro Asai
    • Atsuhiro YamagishiTouru InoueTokumichi MurakamiKohtaro Asai
    • H03M13/17G11C29/00G06F11/10H03M13/00
    • H03M13/17
    • An apparatus for decoding a received BCH code signal for correcting a combined complex error is disclosed which includes a syndrome generating circuit for generating two n-bit syndromes corresponding to the received signal, a syndrome converting circuit for converting the two n-bit syndromes to a 2n-bit syndrome, a random error correcting circuit, a burst error correcting circuit, two combining circuits and output selecting circuit. The random error correcting circuit inputs the two n-bit syndromes and outputs a random error correction signal to one of the combining circuits and the burst error correcting circuit inputs the 2n-bit syndrome and outputs a burst error correction signal to the other of the combining circuits. The combining circuits combine the correction signals to the received BCH code signal. The output selecting circuit selectively outputs one of the combined signals from the combining circuits in accordance with the decoding conditions of the error correcting circuits and the result of comparison between the decoded and error-corrected signals from the combining circuits.
    • 公开了一种用于解码接收到的用于校正组合复错误的BCH码信号的装置,其包括用于产生对应于接收信号的两个n位校正子的校正子产生电路,用于将两个n位校正子转换为 2n位校正子,随机纠错电路,脉冲串纠错电路,两个组合电路和输出选择电路。 随机误差校正电路输入两个n位校正子,并向合成电路之一输出随机纠错信号,并且脉冲串纠错电路输入2n位校正子,并将脉冲串纠错信号输出到组合中的另一个 电路。 组合电路将校正信号组合到接收的BCH码信号。 输出选择电路根据纠错电路的解码条件和来自组合电路的解码和纠错信号之间的比较结果,有选择地输出来自组合电路的组合信号之一。
    • 82. 发明授权
    • Apparatus for decoding BCH code for correcting complex error
    • 用于解码校正码修正复杂错误的装置
    • US5179560A
    • 1993-01-12
    • US445174
    • 1989-12-04
    • Atsuhiro YamagishiTouru InoueTokumichi MurakamiKohtaro Asai
    • Atsuhiro YamagishiTouru InoueTokumichi MurakamiKohtaro Asai
    • H03M13/17
    • H03M13/17
    • An apparatus for decoding a received BCH code signal for correcting a combined complex error is disclosed which includes a syndrome generating circuit for generating two n-bit syndromes corresponding to the received signal, a syndrome converting circuit for converting the two n-bit syndromes to a 2n-bit syndrome, a random error correcting circuit, a burst error correcting circuit, two combining circuits and output selecting circuit. The random error correcting circuit receives input as the two n-bit syndromes and outputs a random error correction signal to one of the combining circuits and the burst error correcting circuit receives as input the 2n-bit syndrome and outputs a burst error correction signal to the other of the combining circuits. The combining circuits combine the correction signals with the received BCH code signal. The output selecting circuit selectively outputs one of the combined signals from the combining circuits in accordance with the decoding conditions of the error correcting circuits and the result of a comparison between the decoded and error-corrected signals from the combining circuits.
    • 公开了一种用于解码接收到的用于校正组合复错误的BCH码信号的装置,其包括用于产生对应于接收信号的两个n位校正子的校正子产生电路,用于将两个n位校正子转换为 2n位校正子,随机纠错电路,脉冲串纠错电路,两个组合电路和输出选择电路。 随机误差校正电路接收输入作为两个n位校正子,并向组合电路之一输出随机纠错信号,并且脉冲串纠错电路作为输入接收2n位校正子,并将脉冲串纠错信号输出到 其他组合电路。 组合电路将校正信号与接收到的BCH码信号组合。 输出选择电路根据纠错电路的解码条件和来自组合电路的解码和纠错信号之间的比较结果,有选择地输出来自组合电路的组合信号之一。
    • 87. 发明授权
    • Digital watermark embedding device and digital watermark detecting device
    • 数字水印嵌入装置及数字水印检测装置
    • US08406455B2
    • 2013-03-26
    • US12066837
    • 2006-09-27
    • Koichi MagaiHiroshi ItoRyousuke FujiiMitsuyoshi SuzukiKohtaro AsaiTokumichi Murakami
    • Koichi MagaiHiroshi ItoRyousuke FujiiMitsuyoshi SuzukiKohtaro AsaiTokumichi Murakami
    • G06K9/00H04N1/40
    • G06T1/005G06T2201/0051G06T2201/0065G06T2201/0083H04N1/32144H04N1/32203
    • A digital watermark embedding device and a digital watermark detecting device are obtained, which can realize stable digital watermark detection using fewer, and embed and detect a larger amount of digital watermark information with an identical number of pixels used for digital watermark embedding in a conventional technology. The digital watermark embedding device includes: an embedding-information converting unit (103) for converting inputted information to be embedded into a bit string formed of “0's” and “1's” and embedding respective bits of the converted bit string multiple times to output a digital watermark pattern having N −1's or N+1's as elements; an orthogonal-pattern generating unit (105) for generating orthogonal patterns each formed of a combination of elements of −1's and +1's and orthogonal to one another; an integrating unit (109) for integrating each of the orthogonal patterns from the orthogonal-pattern generating unit with each of the elements of the digital watermark pattern from the embedding-information converting unit to generate an embedding pattern; and a digital-watermark embedding unit (107) for embedding embedding pattern from the integrating unit in an input image and outputting an image after embedding information.
    • 获得了一种数字水印嵌入装置和数字水印检测装置,其可以使用较少的数字水印检测来实现稳定的数字水印检测,并且在常规技术中嵌入和检测用于数字水印嵌入的相同数量的像素的较大数量的水印信息 。 数字水印嵌入装置包括:嵌入信息转换单元,用于将要嵌入的输入信息转换成由0和1形成的比特串,并且多次嵌入转换的比特串的各个比特,以输出具有 N -1或N + 1作为元素; 正交图案生成单元,用于产生各自由-1和+1的元素的组合形成并且彼此正交的正交图案; 积分单元,用于将来自正交图案生成单元的每个正交图案与来自嵌入信息转换单元的数字水印图案的每个元素集成以产生嵌入图案; 以及用于将嵌入模式从积分单元嵌入到输入图像中并在嵌入信息之后输出图像的数字水印嵌入单元(107)。