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81. 发明授权

US08318551B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08318551B2
公开(公告)日：2012-11-27
申请号：US12627204
申请日：2009-11-30
申请人： Kengo Akimoto , Toshinari Sasaki
发明人： Kengo Akimoto , Toshinari Sasaki
IPC分类号： H01L21/84 , H01L29/10 , H01L29/12
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/41733 , H01L29/66969
摘要： A gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; a first source electrode layer and a first drain electrode layer over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer; and a second source electrode layer and a second drain electrode layer over the oxide semiconductor layer. A first part, a second part, and a third part of a bottom surface are in contact with the first source electrode layer, the first drain electrode layer, and the gate insulating layer respectively. A first part and a second part of the top surface are in contact with the second source electrode layer and the second drain electrode layer respectively. The first source electrode layer and the first drain electrode layer are electrically connected to the second source electrode layer and the second drain electrode layer respectively.
摘要翻译：衬底上的栅电极层; 栅电极层上的栅极绝缘层; 栅极绝缘层上的第一源极电极层和第一漏极电极层; 栅极绝缘层上的氧化物半导体层; 以及在所述氧化物半导体层上的第二源极电极层和第二漏极电极层。第一部分，第二部分和底部表面的第三部分分别与第一源极电极层，第一漏极电极层和栅极绝缘层接触。上表面的第一部分和第二部分分别与第二源极电极层和第二漏极电极层接触。第一源极电极层和第一漏极电极层分别与第二源极电极层和第二漏极电极层电连接。

82. 发明授权

US08158975B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US08158975B2
公开(公告)日：2012-04-17
申请号：US12575564
申请日：2009-10-08
申请人： Kengo Akimoto
发明人： Kengo Akimoto
IPC分类号： H01L29/10 , H01L29/12 , H01L21/00 , H01L21/16
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/45 , H01L29/78606
摘要： Electric characteristics and reliability of a thin film transistor are impaired by diffusion of an impurity element into a channel region. The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer. A thin film transistor including an oxide semiconductor layer including indium, gallium, and zinc includes source or drain electrode layers in which first conductive layers including aluminum as a main component and second conductive layers including a high-melting-point metal material are stacked. An oxide semiconductor layer 113 is in contact with the second conductive layers and barrier layers including aluminum oxide as a main component, whereby diffusion of aluminum atoms to the oxide semiconductor layer is suppressed.

83. 发明授权

US08158464B2 Method of manufacturing a liquid crystal display device with a semiconductor film including zinc oxide 有权
标题翻译：具有包含氧化锌的半导体膜的液晶显示装置的制造方法
公开(公告)号：US08158464B2
公开(公告)日：2012-04-17
申请号：US12411957
申请日：2009-03-26
申请人： Kengo Akimoto
发明人： Kengo Akimoto
IPC分类号： H01L29/04
CPC分类号： H01L29/7869 , H01L27/1214 , H01L27/1225 , H01L27/1255 , H01L29/41733 , H01L29/45 , H01L29/4908 , H01L29/78621
摘要： To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film.
摘要翻译：为了提供其中不产生缺陷或故障的半导体器件及其制造方法，即使使用ZnO半导体膜，并且将添加有n型或p型杂质的ZnO膜用于源电极和漏电极。半导体器件包括通过栅极绝缘膜上的栅电极，Al膜或Al合金膜上的氧化硅膜或氮氧化硅膜形成的栅极绝缘膜，n型或p型的ZnO膜在Al膜或Al合金膜上添加型杂质，在添加有n型或p型杂质的ZnO膜上的ZnO半导体膜和栅极绝缘膜。

84. 发明授权

US08129719B2 Semiconductor device and method for manufacturing the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08129719B2
公开(公告)日：2012-03-06
申请号：US12549415
申请日：2009-08-28
申请人： Shunpei Yamazaki , Kengo Akimoto
发明人： Shunpei Yamazaki , Kengo Akimoto
IPC分类号： H01L29/12 , H01L21/34 , H01L29/786
CPC分类号： H01L29/78696 , H01L21/02318 , H01L21/02323 , H01L21/0234 , H01L21/02565 , H01L29/247 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/78693
摘要： An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
摘要翻译：本发明的目的是提供一种薄膜晶体管的有利的界面特性，该薄膜晶体管包括氧化物半导体层，而不混入杂质如水分。另一个目的是提供一种包括具有优异的电特性和高可靠性的薄膜晶体管的半导体器件，以及可以以高生产率制造半导体器件的方法。要点是在栅极绝缘层的表面进行氧自由基处理。因此，在栅极绝缘层与半导体层之间的界面处存在氧浓度的峰值，并且栅极绝缘层的氧浓度具有浓度梯度。氧浓度朝向栅极绝缘层和半导体层之间的界面增加。

85. 发明授权

US07952392B2 Logic circuit 有权
标题翻译：逻辑电路
公开(公告)号：US07952392B2
公开(公告)日：2011-05-31
申请号：US12605607
申请日：2009-10-26
申请人： Jun Koyama , Kengo Akimoto , Masashi Tsubuku
发明人： Jun Koyama , Kengo Akimoto , Masashi Tsubuku
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/094 , H01L27/0883 , H01L27/1225 , H03K19/09407 , H03K19/09421 , H03K19/096
摘要： An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.
摘要翻译：目的是将使用氧化物半导体的晶体管施加到包括增强晶体管的逻辑电路。逻辑电路包括耗尽晶体管101和增强晶体管102.晶体管101和102各自包括栅电极，栅极绝缘层，第一氧化物半导体层，第二氧化物半导体层，源电极和漏电极。晶体管102包括在源电极和漏极之间的第一氧化物半导体层中的区域上设置的还原防止层。

86. 发明授权

US07948040B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07948040B2
公开(公告)日：2011-05-24
申请号：US12031893
申请日：2008-02-15
申请人： Shunpei Yamazaki , Kengo Akimoto
发明人： Shunpei Yamazaki , Kengo Akimoto
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/78621 , H01L27/12 , H01L27/1248 , H01L29/42384 , H01L29/458 , H01L29/66757 , H01L2029/7863
摘要： A semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of the semiconductor layer and partially in contact with the impurity region; an insulating layer provided over the gate electrode and the first conductive layer; and a second conductive layer which is formed in the insulating layer and in contact with the first conductive layer through an opening at least part of which overlaps with the first conductive layer.
摘要翻译：半导体器件包括与栅电极重叠并且在与栅电极重叠的区域之外具有杂质区域的半导体层; 第一导电层，其设置在设置有半导体层的栅电极并且部分地与杂质区接触的一侧; 设置在所述栅电极和所述第一导电层上的绝缘层; 以及第二导电层，其形成在所述绝缘层中并且通过其至少一部分与所述第一导电层重叠的开口与所述第一导电层接触。

87. 发明授权

US07923356B2 Semiconductor film, semiconductor device and method for manufacturing same 有权
标题翻译：半导体膜，半导体器件及其制造方法
公开(公告)号：US07923356B2
公开(公告)日：2011-04-12
申请号：US11295470
申请日：2005-12-07
申请人： Toru Takayama , Kengo Akimoto
发明人： Toru Takayama , Kengo Akimoto
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , H01L29/78666 , H01L29/78675
摘要： Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.
摘要翻译：关于具有在基板上使用薄膜晶体管的集成电路的半导体器件的制造方法的技术，存在的问题是提供一种形成具有变形的非晶硅膜的条件。在使用溅射法沉积非晶硅膜的情况下，提供15至25kHz的频率和0.5至3kw的沉积功率的条件。这可以在非晶硅膜中充分地含有10×10 20 / cm 3以上的Ar，因此能够形成具有变形的非晶硅膜。

88. 发明申请

US20100072470A1 DISPLAY DEVICE 有权
标题翻译：显示设备
公开(公告)号：US20100072470A1
公开(公告)日：2010-03-25
申请号：US12556695
申请日：2009-09-10
申请人： Shunpei Yamazaki , Kengo Akimoto , Shigeki Komori , Hideki Uochi , Tomoya Futamura , Takahiro Kasahara
发明人： Shunpei Yamazaki , Kengo Akimoto , Shigeki Komori , Hideki Uochi , Tomoya Futamura , Takahiro Kasahara
IPC分类号： H01L33/00
CPC分类号： H01L29/7869 , H01L27/0266 , H01L27/1225 , H01L27/124
摘要： A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.
摘要翻译：保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅绝缘层上的栅电极重叠的第一氧化物半导体层，与沟道形成区重叠的沟道保护层的第一氧化物半导体层，以及一对第一布线层和第二布线层，其端部与沟道保护层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。因此，可以降低结漏电，提高非线性元件的特性。

89. 发明授权

US07541213B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07541213B2
公开(公告)日：2009-06-02
申请号：US11822924
申请日：2007-07-11
申请人： Kengo Akimoto
发明人： Kengo Akimoto
IPC分类号： H01L21/00
CPC分类号： H01L27/12 , H01L27/105 , H01L27/11293 , H01L27/1214 , H01L27/1266
摘要： The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source region and the drain region; a second interlayer insulating film formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring electrically connected to one of the first electrode and the second electrode, on the second interlayer insulating film; and a second wiring not electrically connected to the other of the first electrode and the second electrode, on the second interlayer insulating film; in which the second wiring is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film.
摘要翻译：半导体器件包括薄膜晶体管; 薄膜晶体管上的第一层间绝缘膜; 在所述第一层间绝缘膜上方电连接到源区和漏区之一的第一电极; 电源地连接到所述源极区域和所述漏极区域中的另一个的第二电极; 形成在第一层间绝缘膜，第一电极和第二电极上的第二层间绝缘膜; 在第二层间绝缘膜上电连接到第一电极和第二电极之一的第一布线; 以及在所述第二层间绝缘膜上不与所述第一电极和所述第二电极中的另一个电连接的第二布线; 其中第二布线不通过形成在第二层间绝缘膜中的分离区域而电连接到第一电极和第二电极中的另一个。

90. 发明授权

US07538238B2 Production method of oil or fat containing polyunsaturated fatty acid-containing triglyceride 有权
标题翻译：含有多不饱和脂肪酸的甘油三酸酯的油脂的生产方法
公开(公告)号：US07538238B2
公开(公告)日：2009-05-26
申请号：US10482373
申请日：2002-07-02
申请人： Kengo Akimoto , Motoo Sumida , Kenichi Higashiyama , Shigeaki Fujikawa
发明人： Kengo Akimoto , Motoo Sumida , Kenichi Higashiyama , Shigeaki Fujikawa
IPC分类号： A23D9/00
CPC分类号： C12P7/6472 , A23C9/1528 , A23C11/04 , A23K20/158 , A23L33/115 , A23L33/12 , C11C3/08 , C11C3/10
摘要： The present invention relates to a production method of an oil containing triglyceride in which medium chain fatty acids are bound to the 1- and 3-positions of the triglyceride and polyunsaturated fatty acid is bound to the 2 position by allowing lipase, which specifically acts on ester bonds at the 1- and 3-positions that has been immobilized on a porous ion exchange resin support having a pore size of about 100 Angstroms or more, to act on a mixture of medium-chain fatty acids and raw material oil containing at least one polyunsaturated fatty acid selected from the group consisting of ω6 series polyunsaturated fatty acid having 18 or more carbon atoms and 3 or more double bonds and ω9 series polyunsaturated fatty acid having 18 or more carbon atoms and 2 or more double bonds, but not containing ω3 series polyunsaturated fatty acid, oils and fats or triglycerides obtained by that method, and the use of the oils and fats or triglycerides in a food, beverage or pharmaceutical composition.
摘要翻译：本发明涉及含有甘油三酯的油的制备方法，其中中链脂肪酸与甘油三酯的1位和3位结合，多不饱和脂肪酸通过使脂肪酶特异性地作用于2位而结合到2位上在固定在孔径为约100埃以上的多孔离子交换树脂载体上的1-位和3-位的酯键作用于中链脂肪酸和至少含有至少一种选自具有18个或更多个碳原子的ω-6系多不饱和脂肪酸和3个或更多个双键的多不饱和脂肪酸和具有18个或更多个碳原子和2个或更多个双键但不含ω3的ω-系列多不饱和脂肪酸系列多不饱和脂肪酸，通过该方法获得的油和脂肪或甘油三酯，以及在食品，饮料或药物中使用油和脂肪或甘油三酸酯 l组成。

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