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81. 发明申请

US20120033506A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120033506A1
公开(公告)日：2012-02-09
申请号：US13204276
申请日：2011-08-05
申请人： Kiyohiro Furutani , Yoshinori Matsui
发明人： Kiyohiro Furutani , Yoshinori Matsui
IPC分类号： G11C5/14 , G11C7/06 , G05F1/10 , G11C7/12
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.
摘要翻译：半导体器件包括内部电路和内部电压产生电路，其产生相对于从外部提供的电源电压的变化而稳定的内部电压并将内部电压提供给内部电路。内部电压产生电路执行控制，使得当电源电压上升到超过预定值时，停止内部电压稳定的操作，以使内部电压随着电源电压的上升而增加。

82. 发明申请

US20110080797A1 SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIERS 有权
标题翻译：具有感应放大器的半导体器件
公开(公告)号：US20110080797A1
公开(公告)日：2011-04-07
申请号：US12897399
申请日：2010-10-04
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C11/4074 , G11C7/02 , G11C11/406 , G11C11/40615 , G11C2211/4068
摘要： A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.
摘要翻译：具有读出放大器并被提供有外部电源电压的半导体器件包括连接到读出放大器的驱动信号线，从外部电源电压产生第一电压的升压电路，第一电压高于外部电源电压和降压电路将外部电源电压降低到第二电压。为了使得读出放大器能够在涉及外部访问的正常模式下执行感测操作，在感测操作的初始阶段将第一电压施加到驱动信号线，此后将第二电压施加到驱动信号线。在不涉及外部访问的刷新模式下，升压电路被关闭，并且第二电压从感测操作的初始阶段施加到驱动信号线。

83. 发明申请

US20070120592A1 Semiconductor device with pump circuit 有权
公开(公告)号：US20070120592A1
公开(公告)日：2007-05-31
申请号：US11699427
申请日：2007-01-30
申请人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
发明人： Minoru Senda , Kiyohiro Furutani , Taku Ogura , Shigehiro Kuge , Satoshi Kawasaki , Tadaaki Yamauchi
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/077 , H03K3/356113
摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

84. 发明授权

US06781900B2 Semiconductor memory device with enhanced reliability 失效
标题翻译：具有增强可靠性的半导体存储器件
公开(公告)号：US06781900B2
公开(公告)日：2004-08-24
申请号：US10234256
申请日：2002-09-05
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo , Shigehiro Kuge
发明人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo , Shigehiro Kuge
IPC分类号： G11C2900
CPC分类号： G11C29/027 , G11C29/02
摘要： The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.
摘要翻译：半导体存储器件具有作为工作模式的形式模式和测试模式。该程序电路包括熔丝元件，其中使用备用存储单元而不是有缺陷存储单元的地址被编程。程序电路确认在测试模式下比在正常模式下更严格的状态下的熔断器的断开状态。在测试模式和正常模式之间的结果不同的情况下，通过检测电路将异常通知给外部。在保险丝没有完全熔断的情况下，也可以在测试模式中检测这样的保险丝以排除有缺陷的芯片。

85. 发明授权

US06551846B1 Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration 失效
标题翻译：半导体存储器能够正确且可靠地实现电压应力加速
公开(公告)号：US06551846B1
公开(公告)日：2003-04-22
申请号：US09642751
申请日：2000-08-18
申请人： Kiyohiro Furutani , Mikio Asakura , Tetsuo Katoh
发明人： Kiyohiro Furutani , Mikio Asakura , Tetsuo Katoh
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/3011 , Y10S257/905 , Y10S257/906 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.
摘要翻译：测试信号发生电路在测试模式操作中从经由地址终端提供的少量信号产生内部测试控制信号。根据测试控制信号，设置来自地址缓冲器的内部行地址信号位的值，而具有测试控制功能的行相关控制电路根据测试控制来控制行选择电路和位线外围电路的操作信号。多个字线被同时驱动到选择状态，并且在短时间段内根据少量的控制信号执行加速度测试。存储单元电容器和字线之间施加的电压应力可以用少量的控制信号加速。

86. 发明授权

US06195298B1 Semiconductor integrated circuit capable of rapidly rewriting data into memory cells 失效
标题翻译：半导体集成电路能够将数据快速重写到存储单元中
公开(公告)号：US06195298B1
公开(公告)日：2001-02-27
申请号：US09499734
申请日：2000-02-08
申请人： Kiyohiro Furutani , Katsuyoshi Mitsui
发明人： Kiyohiro Furutani , Katsuyoshi Mitsui
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C5/147
摘要： A semiconductor integrated circuit includes a node for the power supply voltage for array that is connected to a sense amplifier, a decoupling capacitance connected to the node for the power supply voltage for array, a voltage-down converter connected to the node for the power supply voltage for array and generating a largest voltage stored in a memory cell, and two voltage-down converters connected to the node for the power supply voltage for array and generating a voltage higher than the largest voltage, and boosts the voltage of the node for the power supply voltage for array to attain a voltage higher than the largest voltage in the stand-by state and activates the voltage-down converter generating the largest voltage in operation.
摘要翻译：半导体集成电路包括用于连接到读出放大器的阵列的电源电压的节点，连接到用于阵列的电源电压的节点的去耦电容，连接到用于电源的节点的降压转换器并且产生存储在存储单元中的最大电压，以及两个降压转换器，连接到节点，用于阵列的电源电压，并产生高于最大电压的电压，并将节点的电压升高为用于阵列的电源电压以获得高于待机状态下的最大电压的电压，并激活在工作中产生最大电压的降压转换器。

87. 再颁专利

USRE36932E Semiconductor memory device operating stably under low power supply voltage with low power consumption 有权
标题翻译：半导体存储器件在低电源电压下稳定工作，功耗低
公开(公告)号：USRE36932E
公开(公告)日：2000-10-31
申请号：US221835
申请日：1998-12-28
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C11/413 , G05F1/56 , G05F3/24 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/408 , G11C11/409 , H01L21/822 , H01L27/02 , H01L27/04 , G11C7/00
CPC分类号： H01L27/0218 , G11C11/4074 , G11C5/146 , G11C5/147
摘要： A semiconductor memory device of the present invention includes an internal power supply voltage generating circuit down converting external power supply voltage to generate first and second internal power supply voltages, a Vpp generating circuit generating a high voltage from external power supply voltage by charge pumping operation, and a Vbb generating circuit generating negative voltage from external power supply voltage by charge pumping operation. The first internal supply voltage is applied to a control circuit and a sense amplifier drive signal generating circuit. The second internal power supply voltage is applied to a circuit generating a bit line equalize/precharge signal. Even if the first internal power supply voltage is made small, the Vpp generating circuit and the Vbb generating circuit generate a prescribed voltage from external power supply voltage. Therefore, these circuits generate a prescribed internal high voltage and negative voltage efficiently and stably. The bit line equalize/precharge signal is at a voltage level higher than the first internal power supply voltage. The bit line equalize/precharge signal can equalize/precharge a bit line at a high speed. As a result, a semiconductor memory device which operates stably with low power consumption is provided.
摘要翻译：本发明的半导体存储器件包括：内部电源电压产生电路，其将外部电源电压转换成转换，以产生第一和第二内部电源电压; Vpp产生电路，通过电荷泵送操作从外部电源电压产生高电压，以及通过电荷泵送操作从外部电源电压产生负电压的Vbb发生电路。第一内部电源电压被施加到控制电路和读出放大器驱动信号发生电路。第二内部电源电压被施加到产生位线均衡/预充电信号的电路。即使第一内部电源电压变小，Vpp发生电路和Vbb发生电路也从外部电源电压产生规定的电压。因此，这些电路有效且稳定地产生规定的内部高压和负电压。位线均衡/预充电信号处于比第一内部电源电压高的电压电平。位线均衡/预充电信号可以高速均衡/预充电位线。结果，提供了以低功耗稳定运行的半导体存储器件。

88. 发明授权

US6111805A Power-on-reset circuit for generating a reset signal to reset a DRAM 失效
标题翻译：用于产生复位信号以复位DRAM的上电复位电路
公开(公告)号：US6111805A
公开(公告)日：2000-08-29
申请号：US195688
申请日：1998-11-19
申请人： Kiyohiro Furutani
发明人： Kiyohiro Furutani
IPC分类号： G11C11/407 , G11C11/401 , G11C11/4072 , G11C7/00
CPC分类号： G11C11/4072
摘要： In a signal generating circuit generating a reset signal for resetting a DRAM at the time of turning on the power supply potential, a resistance element is connected between a line of the power supply potential and a node, and two N channel MOS transistors constituting a discharge circuit are connected in series between the node and a line of a ground potential. When the power supply potential is lower than a prescribed potential, the two N channel MOS transistors are rendered non-conductive so that the node attains to the "H" level, and when the power supply potential is higher than the prescribed potential, the two N channel MOS transistors are rendered conductive so that the node attains to the "L" level. Therefore, even when the power supply potential changes moderately, the level of the reset signal changes abruptly, surely resetting the DRAM.
摘要翻译：在产生用于在接通电源电位时复位DRAM的复位信号的信号产生电路中，电源元件连接在电源电位线和节点之间，并且两个N沟道MOS晶体管构成放电电路串联在节点和地电位线之间。当电源电位低于规定电位时，两个N沟道MOS晶体管变得不导通，使得节点达到“H”电平，并且当电源电位高于规定电位时，两个 N沟道MOS晶体管导通，使得节点达到“L”电平。因此，即使电源电位适度变化，复位信号的电平急剧变化，肯定重置DRAM。

89. 发明授权

US6091648A Voltage generating circuit for semiconductor integrated circuit device 有权
标题翻译：用于半导体集成电路器件的电压产生电路
公开(公告)号：US6091648A
公开(公告)日：2000-07-18
申请号：US145141
申请日：1998-09-01
申请人： Kiyohiro Furutani , Katsuyoshi Mitsui
发明人： Kiyohiro Furutani , Katsuyoshi Mitsui
IPC分类号： G11C11/413 , G05F1/56 , G11C5/14 , G11C7/06 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C7/06 , G11C5/147
摘要： A semiconductor integrated circuit includes a node for the power supply voltage for array that is connected to a sense amplifier, a decoupling capacitance connected to the node for the power supply voltage for array, a voltage-down converter connected to the node for the power supply voltage for array and generating a largest voltage stored in a memory cell, and two voltage-down converters connected to the node for the power supply voltage for array and generating a voltage higher than the largest voltage, and boosts the voltage of the node for the power supply voltage for array to attain a voltage higher than the largest voltage in the stand-by state and activates the voltage-down converter generating the largest voltage in operation.
摘要翻译：半导体集成电路包括用于连接到读出放大器的阵列的电源电压的节点，连接到用于阵列的电源电压的节点的去耦电容，连接到用于电源的节点的降压转换器并且产生存储在存储单元中的最大电压，以及两个降压转换器，连接到节点，用于阵列的电源电压，并产生高于最大电压的电压，并将节点的电压升高为用于阵列的电源电压以获得高于待机状态下的最大电压的电压，并激活在工作中产生最大电压的降压转换器。

90. 发明授权

US5999464A Semiconductor memory device and method of checking same for defect 失效
公开(公告)号：US5999464A
公开(公告)日：1999-12-07
申请号：US58885
申请日：1998-04-13
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/24
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

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