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81. 发明授权

US07193260B2 Ferroelectric memory device 有权
标题翻译：铁电存储器件
公开(公告)号：US07193260B2
公开(公告)日：2007-03-20
申请号：US10883736
申请日：2004-07-06
申请人： Masahiro Kamoshida , Daisaburo Takashima
发明人： Masahiro Kamoshida , Daisaburo Takashima
IPC分类号： H01L27/108
CPC分类号： H01L27/11502 , H01L27/0207 , H01L27/11507
摘要： A ferroelectric memory device includes a first bit line, a second bit line provided adjacent to the first bit line, a first memory cell block including a first terminal, a second terminal, and a plurality of memory cells connected in series between the first and second terminals and arranged in a first direction along the first bit line connected to the first terminal by a first block select transistor, a second memory cell block including a plurality of memory cells, and a plurality of first contacts arranged between the first and second memory cell blocks, each first contact connecting the upper electrode and drain or source electrode of one memory cell.
摘要翻译：铁电存储器件包括第一位线，与第一位线相邻设置的第二位线，第一存储器单元块，包括第一端子，第二端子和多个存储单元，串联连接在第一和第二位线之间端子，并且通过第一块选择晶体管沿着与第一端子连接的第一位线的第一方向布置，包括多个存储单元的第二存储单元块以及布置在第一和第二存储单元之间的多个第一触点每个第一触点连接一个存储单元的上电极和漏极或源电极。

82. 发明申请

US20070058420A1 POWER SUPPLY VOLTAGE CONTROL CIRCUIT 失效
标题翻译：电源电压控制电路
公开(公告)号：US20070058420A1
公开(公告)日：2007-03-15
申请号：US11531163
申请日：2006-09-12
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/22
摘要： A power supply voltage control circuit supplying a power supply voltage to a memory cell array, including word lines extending along row direction, bit lines extending along column direction, plate lines extending along the row direction, and a plurality of unit cells disposed at intersections of word lines and bit lines, includes a word line control circuit for supplying a first voltage to the word lines; and a plate line control circuit for supplying a second voltage to the plate lines; and the power supply voltage control circuit provides an amount of current flow from the first voltage so as to keep the first voltage potential almost constant during increasing a value of the second voltage in a power-on sequence, firstly increasing a value of the higher voltage of two potential voltages: the first voltage and the second voltage capacitive coupled, and then increasing a value of the lower second voltage.
摘要翻译： 1.一种电源电压控制电路，其向存储单元阵列供给电源电压，所述电源电压包括沿着行方向延伸的字线，沿着列方向延伸的位线，沿着行方向延伸的板条，以及设置在字线和位线包括用于向字线提供第一电压的字线控制电路; 以及板线控制电路，用于向所述板线提供第二电压; 并且电源电压控制电路提供从第一电压的电流量，以便在增加通电序列中的第二电压的值时，保持第一电压电位几乎恒定，首先增加较高电压的值的两个电位电压：第一电压和第二电压电容耦合，然后增加较低的第二电压的值。

83. 发明申请

US20070008765A1 Ferroelectric random access memory 有权
标题翻译：铁电随机存取存储器
公开(公告)号：US20070008765A1
公开(公告)日：2007-01-11
申请号：US11220853
申请日：2005-09-08
申请人： Daisaburo Takashima
发明人： Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one-end side in a column direction every four cell blocks sequentially adjacent to each other in a row direction. One ends of the four cell blocks are connected to four different plate lines, respectively, and the other ends of the four cell blocks are connected to four different bit lines through four block selection transistors, respectively. Of the four bit lines, two bit lines constitute a first bit line pair, and the two remaining bit lines constitute a second bit line pair. Any one of the first and second bit line pairs is connected to the sense amplifier circuit and the other bit line pair is connected at a constant voltage.
摘要翻译：通过将铁电电容器并联连接到晶体管而获得的四个存储单元彼此串联连接以构成单元块。读出放大器电路在行方向上彼此顺序相邻的四个单元块在列方向的一端侧配置。四个单元块的一端分别连接到四个不同的板线，并且四个单元块的另一端分别通过四个块选择晶体管连接到四个不同的位线。在四个位线中，两个位线构成第一位线对，并且其余两个位线构成第二位线对。第一和第二位线对中的任一个连接到读出放大器电路，另一个位线对以恒定电压连接。

84. 发明授权

US07064972B2 Ferroelectric memory device and read control method thereof 失效
标题翻译：铁电存储器件及其读取控制方法
公开(公告)号：US07064972B2
公开(公告)日：2006-06-20
申请号：US10403120
申请日：2003-04-01
申请人： Daisaburo Takashima
发明人： Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device is disclosed, which includes a memory cell array which is formed of a matrix layout of memory cells each having a transistor with its gate connected to a word line and a ferroelectric capacitor having one end connected to a bit line and the other end connected to a plate line, a plate-line drive circuit for driving the plate line, a word-line drive circuit for driving the word line, and a sense amplifier connected to the bitline for detecting and amplifying memory cell data. At least one of the plateline drive circuit and said wordline drive circuit has a pullup circuit operable to potentially raise or boost an output terminal of this at least one circuit from a low level up to a high level and a pulldown circuit for letting the output terminal potentially drop from the high level down to the low level. At least one of the pullup and pulldown circuits is arranged to be variable in driving ability or “drivability” during its driving operation.
摘要翻译：公开了一种铁电存储器件，其包括存储单元阵列，该存储单元阵列由存储单元的矩阵布局形成，每个存储单元具有其栅极连接到字线的晶体管和一端连接到位线的铁电电容器，另一端连接到位线端板连接到板线，用于驱动板线的板线驱动电路，用于驱动字线的字线驱动电路，以及连接到位线的用于检测和放大存储器单元数据的读出放大器。平板驱动电路和所述字线驱动电路中的至少一个具有上拉电路，其可操作以将该至少一个电路的输出端子从低电平升高或升高到高电平，并且用于使输出端子有可能从高位下降到低水平。上拉和下拉电路中的至少一个被布置成在其驱动操作期间具有可变的驱动能力或“驾驶性能”。

85. 发明授权

US07061788B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07061788B2
公开(公告)日：2006-06-13
申请号：US11037109
申请日：2005-01-19
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A semiconductor storage device comprises first and second memory cells, each connected to the first pair of word line and bit line and a second pair of word line and bit line, a sense amplifier connected between the first and second bit lines, a first capacitor whose storage electrode being connected to the first bit line, a second capacitor whose storage electrode being connected to the second bit line, first and second wires respectively connected to the first and second plate electrodes of the first and second capacitors, wherein the first and second bit lines are in a complementary relation, and when “0” is read to the first bit line, the first capacitor has an operation to increase a potential of the first plate electrode through the first wire before the sense amplifier operates.
摘要翻译：半导体存储装置包括第一和第二存储单元，每个存储单元连接到第一对字线和位线，第二对字线和位线，连接在第一和第二位线之间的读出放大器，第一电容器，存储电极连接到第一位线，第二电容器，其存储电极连接到第二位线，第一和第二线分别连接到第一和第二电容器的第一和第二平板电极，其中第一和第二位线是互补关系的，并且当对第一位线读取“0”时，第一电容器具有在读出放大器操作之前通过第一引线增加第一平板电极的电位的操作。

86. 发明申请

US20060067100A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20060067100A1
公开(公告)日：2006-03-30
申请号：US11037109
申请日：2005-01-19
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/24
CPC分类号： G11C11/22
摘要： A semiconductor storage device comprises first and second memory cells, each connected to the first pair of word line and bit line and a second pair of word line and bit line, a sense amplifier connected between the first and second bit lines, a first capacitor whose storage electrode being connected to the first bit line, a second capacitor whose storage electrode being connected to the second bit line, first and second wires respectively connected to the first and second plate electrodes of the first and second capacitors, wherein the first and second bit lines are in a complementary relation, and when “0” is read to the first bit line, the first capacitor has an operation to increase a potential of the first plate electrode through the first wire before the sense amplifier operates.
摘要翻译：半导体存储装置包括第一和第二存储单元，每个存储单元连接到第一对字线和位线，第二对字线和位线，连接在第一和第二位线之间的读出放大器，第一电容器，存储电极连接到第一位线，第二电容器，其存储电极连接到第二位线，第一和第二线分别连接到第一和第二电容器的第一和第二平板电极，其中第一和第二位线是互补关系的，并且当对第一位线读取“0”时，第一电容器具有在读出放大器操作之前通过第一引线增加第一平板电极的电位的操作。

87. 发明申请

US20060023484A1 Ferroelectric random access memory device 失效
标题翻译：铁电随机存取存储器件
公开(公告)号：US20060023484A1
公开(公告)日：2006-02-02
申请号：US11046878
申请日：2005-02-01
申请人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
发明人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/14
摘要： A plurality of ferroelectric memory cells is arrayed. One terminal of each memory cells arrayed in the same column is connected in common to a first bit line. A gate of a transistor of memory cells arrayed in the same row is connected in common to a word line. The other terminal of each of memory cells arrayed in the same column or the same row is connected in common to a cell plate line. A second bit line is connected with a reference voltage supply circuit. The first and second bit lines are connected with a data read circuit. The data read circuit includes a sense amplifier and a current mirror circuit having a pair of current input node connected to the first and second bit lines, and carrying the same current flowing through one of the first and second bit line to the other bit line.
摘要翻译：排列多个铁电存储单元。排列在同一列中的每个存储单元的一个端子共同连接到第一位线。排列在同一行中的存储单元的晶体管的栅极共同连接到字线。排列在同一列或同一行中的每个存储单元的另一个端子共同连接到单元格板线。第二位线与参考电压供应电路连接。第一和第二位线与数据读取电路连接。数据读取电路包括读出放大器和电流镜像电路，其具有连接到第一和第二位线的一对电流输入节点，并且将流过第一和第二位线之一的相同电流传送到另一位线。

88. 发明申请

US20050146918A1 Semiconductor device having semiconductor memory with sense amplifier 有权
公开(公告)号：US20050146918A1
公开(公告)日：2005-07-07
申请号：US11059569
申请日：2005-02-17
申请人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
发明人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
IPC分类号： G11C7/06 , G11C11/22
CPC分类号： G11C7/04 , G11C7/062 , G11C7/067 , G11C11/22
摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.

89. 发明申请

US20050128780A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050128780A1
公开(公告)日：2005-06-16
申请号：US10830046
申请日：2004-04-23
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： There is disclosed a semiconductor integrated circuit device comprising a memory cell array including a memory cell having a ferroelectric capacitor having first and second electrodes. A first bit line is electrically connected to the first electrode. A first potential generation circuit supplies a first potential to the second electrode to apply a voltage which drops at a first rate of change with a rise of temperature to the ferroelectric capacitor. A sense amplifier amplifies a potential difference between the first bit line and a second bit line complementary to the first bit line.
摘要翻译：公开了一种半导体集成电路器件，包括存储单元阵列，该存储单元阵列包括具有第一和第二电极的铁电电容器的存储单元。第一位线电连接到第一电极。第一电位产生电路向第二电极提供第一电位，以施加以第一变化率下降的电压随着温度上升到铁电电容器。读出放大器放大第一位线和与第一位线互补的第二位线之间的电位差。

90. 发明申请

US20050002247A1 Shared sense amplifier scheme semiconductor memory device and method of testing the same 失效
公开(公告)号：US20050002247A1
公开(公告)日：2005-01-06
申请号：US10679455
申请日：2003-10-07
申请人： Masahiro Kamoshida , Daisaburo Takashima
发明人： Masahiro Kamoshida , Daisaburo Takashima
IPC分类号： G01R31/28 , G11C7/06 , G11C7/18 , G11C11/22 , G11C29/34 , G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C2207/005
摘要： A semiconductor memory device includes first and second select transistors arranged on both sides of a shared-scheme sense amplifier and connected to a bit line, and first and second memory cell arrays connected to the bit line via the first and second select transistors, respectively, the first and second memory cell arrays each including a plurality of memory cells each having a cell transistor and a ferroelectric capacitor. The device further includes a setting circuit which controls the first and second select transistors, thereby setting the first and second memory cell arrays in an operative state at the same time, and a control circuit which performs a test at the same time for the first and second memory cell arrays, which are set in the operative state at the same time by the setting circuit.

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